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w78erd2/w78erd2a data sheet 8-bit microcontroller publication release date: february 14, 2007 - 1 - revision a10 table of contents- 1. general des cription ......................................................................................................... 3 2. features ....................................................................................................................... .......... 3 3. pin configura tions ............................................................................................................ 4 4. pin descri ption................................................................................................................ ..... 5 5. functional des cription ................................................................................................... 6 5.1 ram ............................................................................................................................ .... 6 5.2 timers/count ers ............................................................................................................. 6 5.3 clock .......................................................................................................................... ..... 7 5.4 power m anagement ........................................................................................................ 7 5.5 reduce emi em ission .................................................................................................... 7 5.6 reset.......................................................................................................................... ..... 7 6. special function register.............................................................................................. 8 7. port 4 and base addr ess regist ers ......................................................................... 30 8. interrup ts ..................................................................................................................... ...... 32 8.1 external interr upts 2 and 3 ........................................................................................... 32 8.2 interrupt pr iority ............................................................................................................ 3 2 9. programmable time rs/count ers ............................................................................... 33 9.1 timer 0 and ti mer 1 ..................................................................................................... 33 9.2 timer/count er 2............................................................................................................ 35 10. enhanced full dupl ex serial port............................................................................ 38 10.1 mode 0 ........................................................................................................................ 3 8 10.2 mode 1 ........................................................................................................................ 3 9 10.3 mode 2 ........................................................................................................................ 4 0 10.4 mode 3 ........................................................................................................................ 4 1 10.5 framing error detection ............................................................................................... 42 10.6 multi-processor communica tions................................................................................. 42 11. programmable counter array (p ca) ........................................................................ 44 11.1 pca captur e mode ....................................................................................................... 47 11.2 16-bit software timer comparator mode ..................................................................... 47 11.3 high speed out put mode ............................................................................................. 48 11.4 pulse width modul ator m ode ....................................................................................... 49 11.5 watchdog ti mer ........................................................................................................... 49 12. hardware watchdog timer (one-tim e enabled with reset-out) ................... 50
w78erd2/w78erd2a - 2 - 13. dual dp tr...................................................................................................................... ........ 50 14. timed-access pr otection .............................................................................................. 51 15. in-system programmi ng (isp) mode ............................................................................ 53 16. h/w reboot mode (b oot from ldrom) ........................................................................ 57 17. option bits register ........................................................................................................ 58 18. electrical chara cteristi cs......................................................................................... 60 18.1 absolute maxi mum rati ngs .......................................................................................... 60 18.2 d.c. characte ristic s...................................................................................................... 60 18.3 a.c. characte ristic s ...................................................................................................... 62 19. timing w aveforms ............................................................................................................. 64 20. typical applicat ion circui ts ........................................................................................ 66 20.1 external program me mory and cr ystal ........................................................................ 66 20.2 expanded external data me mory and osc illator ......................................................... 67 21. package dime nsions ......................................................................................................... 68 22. applicatio n no te ............................................................................................................... 70 22.1 in-system programming (isp) software ex amples ..................................................... 70 22.2 how to use programmabl e counter array ................................................................... 74 23. revision history ............................................................................................................... .75
w78erd2/w78erd2a publication release date: february 14, 2007 - 3 - revision a10 1. general description the w78erd2 is an 8-bit microcontroller which is pin- and instruction-set-compatible with the standard 80c52. the w78erd2 contains a 64-kb flash eprom whose contents may be updated in- system by a loader program stored in an auxilia ry, 4-kb flash eprom. once the contents are confirmed, it can be protected for security. the w78erd2 also contains 256 bytes of on-chip ram; 1 kb of auxiliary ram; four 8-bit, bi- directional and bit-addressable i/o ports; an additional 4-bit port p4; three 16-bit timer/counters; and a serial port. these peripherals are all supported by ni ne interrupt sources with 4 levels of priority. the w78erd2 has two power-reduction modes: idle mode and power-down mode, both of which are software-selectable. idle mode turns off the proc essor clock but allows peripherals to continue operating, while power-down mode stops the crysta l oscillator for minimum power consumption. power-down mode can be activated at any time and in any state without affe cting the processor. 2. features ? 8-bit cmos microcontroller ? pin-compatible with standard 80c52 ? instruction-set compatible with 80c52 ? four 8-bit i/o ports; port 0 has inte rnal pull-up resisters enabled by software. ? one extra 4-bit i/o port with in terrupt and chip-select functions ? three 16-bit timers ? programmable clock out ? programmable counter array (pca) with pw m, capture, compare and watchdog functions ? 9 interrupt sources with 4 levels of priority ? full-duplex serial port with framing-e rror detection and automatic address recognition ? 64-kb, in-system-programmable, flash eprom (ap flash epraom) ? 4-kb auxiliary flash eprom for loader program (ld flash eprom) ? 256-byte on-chip ram ? 1-kb auxiliary ram, software-selectable ? software reset ? 12 clocks per machine cycle operat ion (default). speed up to 40 mhz. ? 6 clocks per machine cycle operation se t by the writer. speed up to 20 mhz. ? 2 dptr registers ? low emi (inhibit ale) ? built-in power management with idle mode and power down mode ? code protection ? packages: ? lead free (rohs) dip 40: w78erd2a40dl ? lead free (rohs) plcc 44: w78erd2a40pl ? lead free (rohs) pqfp 44: w78erd2a40fl
w78erd2/w78erd2a - 4 - 3. pin configurations vdd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 39 40 34 35 36 37 38 30 31 32 33 26 27 28 29 21 22 23 24 25 p0.0, ad0 p0.1, ad1 p0.2, ad2 p0.3, ad3 p0.4, ad4 p0.5, ad5 p0.6, ad6 p0.7, ad7 ea ale psen p2.5, a13 p2.6, a14 p2.7, a15 p2.0, a8 p2.1, a9 p2.2, a10 p2.3, a11 p2.4, a12 t2, p1.0 40-pin dip p1.2 p1.3 p1.4 p1.5 p1.6 rxd, p3.0 txd, p3.1 p1.7 rst int0, p3.2 int1, p3.3 t0, p3.4 t1, p3.5 wr, p3.6 rd, p3.7 xtal1 xtal2 vss t2ex, p1.1 44-pin plcc 40 2 1 44 43 42 41 6543 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 10 9 8 7 14 13 12 11 16 15 p1.5 p1.6 p1.7 rst rxd, p3.0 txd, p3.1 int0, p3.2 int1, p3.3 t0, p3.4 t1, p3.5 a d 3 , p 0 . 3 t 2 , p 1 . 0 p 1 . 2 v d d a d 2 , p 0 . 2 a d 1 , p 0 . 1 a d 0 , p 0 . 0 t 2 e x , p 1 . 1 p 1 . 3 p 1 . 4 x t a l 1 v s s p 2 . 4 , a 1 2 p 2 . 3 , a 1 1 p 2 . 2 , a 1 0 p 2 . 1 , a 9 p 2 . 0 , a 8 x t a l 2 p 3 . 7 , / r d p 3 . 6 , / w r p0.4, ad4 p0.5, ad5 p0.6, ad6 p0.7, ad7 ea ale psen p2.7, a15 p2.6, a14 p2.5, a13 p4.1 p 4 . 0 int2, p4.3 / i n t 3 , p 4 . 2 44-pin qfp 34 40 39 38 37 36 35 44 43 42 41 33 32 31 30 29 28 27 26 25 24 23 p0.4, ad4 p0.5, ad5 p0.6, ad6 p0.7, ad7 ea ale psen p2.7, a15 p2.6, a14 p2.5, a13 22 21 20 19 18 17 16 15 14 13 12 11 4 3 2 1 8 7 6 5 10 9 p1.5 p1.6 p1.7 rst rxd, p3.0 txd, p3.1 int0, p3.2 int1, p3.3 t0, p3.4 t1, p3.5 x t a l 1 v s s p 2 . 4 , a 1 2 p 2 . 3 , a 1 1 p 2 . 2 , a 1 0 p 2 . 1 , a 9 p 2 . 0 , a 8 x t a l 2 p 3 . 7 , / r d p 3 . 6 , / w r a d 3 , p 0 . 3 t 2 , p 1 . 0 p 1 . 2 v d d a d 2 , p 0 . 2 a d 1 , p 0 . 1 a d 0 , p 0 . 0 t 2 e x , p 1 . 1 p 1 . 3 p 1 . 4 p 4 . 0 / i n t 3 , p 4 . 2 p4.1 int2, p4.3
w78erd2/w78erd2a publication release date: february 14, 2007 - 5 - revision a10 4. pin description symbol type* descriptions ea i external access enable: this pin forces the processor to execute instructions in external rom. t he rom address and data are not presented on the bus if the e a pin is high. psen o h program store enable: psen indicates external rom data is on the port 0 address/data bus. if internal rom is accessed, no psen strobe signal is present on this pin. ale o h a ddress latch enable: ale is used to enable the address latch that separates the address from the data on po rt 0. ale runs at 1/6th of the oscillator frequency. rst i l reset: if this pin is set high for two ma chine cycles while the oscillator is running, the w78erd2 is reset. xtal1 i crystal 1: crystal oscillato r input or external clock input. xtal2 o crystal 2: crystal oscillator output. v ss i ground: ground potential. v dd i power supply: supply voltage for operation. p0.0 ? p0.7 i/o d port 0: 8-bit, bi-directional i/o port, the same as that of the standard 80c52. port 0 has internal pull-up resisters enabled by software. p1.0 ? p1.7 i/o h port 1: 8-bit, bi-directional i/o port, the same as that of the standard 80c52. p2.0 ? p2.7 i/o h port 2: 8-bit, bi-directional i/o port wi th internal pull-ups. this port also provides the upper address bits when accessing external memory. p3.0 ? p3.7 i/o h port 3: 8-bit, bi-directional i/o port, the same as that of the standard 80c52. p4.0 ? p4.3 i/o h port 4: 4-bit, bi-directional i/o port with chip-select functions. * note: type i: input, o: output, i/o: bi-directional, h: pull-high, l: pull-low, d: open drain
w78erd2/w78erd2a - 6 - 5. functional description the w78erd2 architecture consists of a core processor that supports 111 different op-codes and references 64 kb of program space and 64 kb of dat a space. it is surrounded by various registers; four general-purpose i/o ports; one s pecial-purpose, programmable, 4- bit i/o port; 256 bytes of ram; 1 kb of auxiliary ram (aux-ram); three timer/c ounters; a serial port; and an internal 74373 latch and 74244 buffer which can be switched to port 2. this section introduces the ram, timers/c ounters, clock, power management, reduce emi emission, and reset. 5.1 ram the w78erd2 has two banks of ram: 256 bytes of ram and 1 kb of aux-ram. aux-ram is enabled by clearing bit 1 in the auxr register, and it is enabled after reset. different addresses in ram are addressed in different ways. ? ram 00h ? 7fh can be addressed directly or indirectly , as in the 8051. the address pointers are r0 and r1 of the selected bank. ? ram 80h ? ffh can only be addressed indirectly, as in the 8051. the address pointers are r0 and r1 of the selected bank. ? aux-ram 00h ? 3ffh is addressed indirectly in the same way external data memory is accessed with the movx instruction. the address pointers are r0 and r1 of the selected bank and the dptr register. ? addresses higher than 3ffh are stored in exter nal memory and are accessed indirectly with the movx instruction, as in the 8051. when aux-ram is enabled, the instruction "mo vx @ri" always accesses aux-ram. when the w78erd2 is executing instructions from inte rnal program memory, accessing aux-ram does not affect ports p0, p2, wr or rd . for example, anl auxr,#11111101b ; enable aux-ram mov dptr,#1234h mov a,#56h movx @dptr,a ; write 56h to address 1234h in external memory mov xramah,#02h ; only 2 lsb effective mov r0,#34h mov a,@r0 ; read aux-ram data at address 0234h 5.2 timers/counters the w78erd2 has three timers/counters called timer 0, timer 1, and timer 2. each timer/counter consists of two 8-bit data registers: tl0 and th 0 for timer 0, tl1 and th1 for timer 1, and tl2 and th2 for timer 2. the operations of timer 0 and timer 1 are similar to those in the w78c52, and these timers are controlled by the tcon and tmod registers.
w78erd2/w78erd2a publication release date: february 14, 2007 - 7 - revision a10 timer 2 is controlled by the t2con register. like timers 0 and 1, timer 2 can operate as either an external event counter or an internal timer, dependi ng on the setting of bit c/t2 in t2con. timer 2 has three operating modes: capture, auto-reload, and baud rate generator. in capture or auto-reload mode, rcap2h and rcap2l are the reload / capture registers and the clock speed is the same as that of timers 0 and 1. 5.3 clock the w78erd2 is designed for either a crys tal oscillator or an external clock. the w78erd2 incorporates a built-in crystal oscillato r. to make the oscillator work, a crystal must be connected across pins xtal1 and xtal2, and a load capacitor may be connected from each pin to ground. in addition, if the crystal frequency is hi gher than 24 mhz, a resistor should be connected between xtal1 and xtal2 to provide a dc bias. an external clock is connected to pin xtal1, while pin xtal2 should be left disconnected. the xtal1 input is a cmos-type input, as required by the crystal oscillator. as a result, the logic-1 voltage should be higher than 3.5 v. 5.4 power management the w78erd2 provides two modes, idle mode and pow er-down mode, to reduce power consumption. both modes are entered by software. the w78erd2 enters idle mode when the idl bit in the pcon register is set. in idle mode, the internal clock for the processor stops while the in ternal clock for the peripherals and interrupt logic continues to run. the w78erd2 leaves idle mode when an interrupt or a reset occurs. the w78erd2 enters power-down mode when the pd bi t in the pcon register is set. in power- down mode, all of the clocks ar e stopped, including the oscillator. the w78erd2 leaves power-down mode when there is a hardware reset or by external interrupts int0 or int1 , if enabled. 5.5 reduce emi emission if the crystal frequency is less than 25 mhz, set bit 7 in the option register to 0 to reduce emi emissions. please see option bits for more information. 5.6 reset the external reset signal is sampled at s5p2. to take effect, it must be held high for at least two machine cycles while the oscillator is running, as the w78erd2 has a special glitch-removal circuit that ignores glitches on the reset line. during reset, the ports are initialized to ffh, the sta ck pointer to 07h, and all of the other sfr to 00h, with two exceptions?sbuf does not change, and bit 4 in pcon is not cleared.
w78erd2/w78erd2a - 8 - 6. special function register the following table identifies the special function r egisters (sfrs) in the w78erd2, as well as each of their addresses and reset values. f8 ch 00000000 ccap0h 00000000 ccap1h 00000000 ccap2h 00000000 ccap3h 00000000 ccap4h 00000000 ff f0 +b 00000000 chpenr 00000000 f7 e8 +p4 xxxx1111 cl 00000000 ccap0l 00000000 ccap1l 00000000 ccap2l 00000000 ccap3l 00000000 ccap4l 00000000 ef e0 +acc 00000000 e7 d8 ccon x0000000 cmod 00xxx000 ccapm0 x0000000 ccapm1 x0000000 ccapm2 x0000000 ccapm3 x0000000 ccapm4 x0000000 ckcon xx000xx1 df d0 +psw 00000000 d7 c8 +t2con 00000000 t2mod xxxxxx00 rcap2l 00000000 rcap2h 00000000 tl2 00000000 th2 00000000 cf c0 xicon 00000000 xiconh 0xxx0xxx p4cona 00000000 p4conb 00000000 sfral 00000000 sfrah 00000000 sfrfd 00000000 sfrcn 00000000 c7 b8 +ip x0000000 saden 00000000 chpcon 000xx000 bf b0 +p3 00000000 p43al 00000000 p43ah 00000000 iph x0000000 b7 a8 +ie 00000000 saddr 00000000 p42al 00000000 p42ah 00000000 p4csin 00000000 af a0 +p2 11111111 xramah 00000000 auxr1 xxxxx0x0 wdtrst 00000000 a7 98 +scon 00000000 sbuf xxxxxxxx p2eal 00000000 p2eah 00000000 9f 90 +p1 11111111 p41al 00000000 p41ah 00000000 97 88 +tcon 00000000 tmod 00000000 tl0 00000000 tl1 00000000 th0 00000000 th1 00000000 auxr 00000000 8f 80 +p0 11111111 sp 00000111 dpl 00000000 dph 00000000 p40al 00000000 p40ah 00000000 port 00000000 pcon 00110000 87 notes: 1. sfrs marked with a plus sign (+) are both byte- and bit-addressable. 2. the text of sfr with bold type char acters are extension function registers. the rest of this section explains each sfr, starting with the lowest address.
w78erd2/w78erd2a publication release date: february 14, 2007 - 9 - revision a10 port 0 bit: 7 6 5 4 3 2 1 0 p0.7 p0.6 p0.5 p0.4 p0.3 p0.2 p0.1 p0.0 mnemonic: p0 address: 80h port 0 is an open-drain, bi-directional i/o port afte r chip is reset. besides, it has internal pull-up resisters enabled by setting p0up of popt (86h) to hi gh. this port also provides a multiplexed, low- order address/data bus when the w78ird2 accesses external memory. stack pointer bit: 7 6 5 4 3 2 1 0 sp.7 sp.6 sp.5 sp.4 sp.3 sp.2 sp.1 sp.0 mnemonic: sp address: 81h the stack pointer stores the ram address (scrat chpad ram, not aux-ram) where the stack begins. it always points to the top of the stack. data pointer low bit: 7 6 5 4 3 2 1 0 dpl.7 dpl.6 dpl.5 dpl.4 dpl.3 dpl.2 dpl.1 dpl.0 mnemonic: dpl address: 82h this is the low byte of the standard-8052 16-bit data pointer. data pointer high bit: 7 6 5 4 3 2 1 0 dph.7 dph.6 dph.5 dph.4 dph.3 dph.2 dph.1 dph.0 mnemonic: dph address: 83h this is the high byte of t he standard-8052 16-bit data pointer. port 4.0 low-address comparator bit: 7 6 5 4 3 2 1 0 p40al.7 p40al.6 p40al.5 p40al. 4 p40al.3 p40al.2 p40al.1 p40al.0 mnemonic: p40al address: 84h port 4.0 high-address comparator bit: 7 6 5 4 3 2 1 0 p40ah.7 p40ah.6 p 40ah.5 p40ah.4 p40ah.3 p40a h.2 p40ah.1 p40ah.0 mnemonic: p40ah address: 85h
w78erd2/w78erd2a - 10 - port option register bit: 7 6 5 4 3 2 1 0 - - - - - - - p0up mnemonic: popt address: 86h bit name function 1 ? 7 - reserve 0 p0up 0: port 0 pins are open-drain. 1: port 0 pins are internally pulled-up. port 0 is structurally the same as port 2. power control bit: 7 6 5 4 3 2 1 0 smod smod0 - por gf1 gf0 pd idl mnemonic: pcon address: 87h bit name function 7 smod 1: double the serial-port baud rate in serial port modes 1, 2, and 3. 6 smod0 0: framing error detection disable. scon.7 acts as per the standard 8052 function. 1: framing error detection enable. scon .7 indicates a frame error and acts as the fe (fe_1) flag. 5 - reserved 4 pof this bit is set to 1 when a power-on reset has occurred. it can be cleared by software. 3 gf1 general-purpose flag. 2 gf0 general-purpose flag. 1 pd set this bit to 1 to go into power down mode. 0 idl set this bit to 1 to go into idle mode. timer control bit: 7 6 5 4 3 2 1 0 tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 mnemonic: tcon address: 88h
w78erd2/w78erd2a publication release date: february 14, 2007 - 11 - revision a10 bit name function 7 tf1 timer 1 overflow flag: this bit is se t when timer 1 overflows. it is cleared automatically when the program does a timer 1 interrupt service routine. it can also be set or cleared by software. 6 tr1 1: turn on timer 1. 0: turn off timer 1. 5 tf0 timer 0 overflow flag: this bit is se t when timer 0 overflows. it is cleared automatically when the program does a timer 0 interrupt service routine. it can also be set or cleared by software. 4 tr0 1: turn on timer 0. 0: turn off timer 0. 3 ie1 interrupt 1 edge detect: this bit is se t by the hardware when a falling-edge / low- level is detected on int1 . if int1 is edge-triggered, this bit is cleared by the hardware when the interrupt service routi ne begins. otherwise, it follows the pin. 2 it1 interrupt 1 type control 1: interrupt 1 is triggered by a falling-edge on int1 . 0: interrupt 1 is triggered by a low-level on int1 . 1 ie0 interrupt 0 edge detect: this bit is se t by the hardware when a falling-edge / low- level is detected on int0 . if int0 is edge-triggered, this bit is cleared by the hardware when the interrupt service routi ne begins. otherwise, it follows the pin. 0 it0 interrupt 0 type control 1: interrupt 0 is triggered by a falling-edge on int0 . 0: interrupt 0 is triggered by a low-level on int0 . timer mode control bit: 7 6 5 4 3 2 1 0 gate t c/ m1 m0 gate t c/ m1 m0 mnemonic: tmod address: 89h bit name function 7 gate gating control: when this bit is set, timer/counter 1 is enabled only while the int1 pin is high and the tr1 control bit is set. when cleared, the int1 pin has no effect, and timer 1 is enabled whenever tr1 is set. 6 t c/ timer or counter select: when cleared, ti mer 1 is incremented by the internal clock. when set, timer 1 counts falling edges on the t1 pin. 5 m1 timer 1 mode select bits: see below. 4 m0 timer 1 mode select bits: see below.
w78erd2/w78erd2a - 12 - continued bit name function 3 gate gating control: when this bit is set, timer/counter 0 is enabled only while the int0 pin is high and the tr0 control bit is set. when cleared, the int0 pin has no effect, and timer 0 is enabled whenever tr0 is set. 2 t c/ timer or counter select: when cleared, ti mer 0 is incremented by the internal clock. when set, timer 0 counts falling edges on the t0 pin. 1 m1 timer 0 mode select bits: see below. 0 m0 timer 0 mode select bits: see below. m1, m0: mode select bits: m1 m0 mode 0 0 mode 0: 8048 timer, tlx serves as 5-bit pre-scale. 0 1 mode 1: 16-bit timer/counter, no pre-scale. 1 0 mode 2: 8-bit timer/counter with auto-reload from thx 1 1 mode 3: (timer 0) tl0 is an 8-bit timer/counter controlled by the standard timer-0 control bits. th0 is an 8-bit timer only c ontrolled by timer-1 control bits. (timer 1) timer/counter 1 is stopped. timer 0 lsb bit: 7 6 5 4 3 2 1 0 tl0.7 tl0.6 tl0.5 tl0.4 tl0.3 tl0.2 tl0.1 tl0.0 mnemonic: tl0 address: 8ah tl0.7-0: timer 0 low byte timer 1 lsb bit: 7 6 5 4 3 2 1 0 tl1.7 tl1.6 tl1.5 tl1.4 tl1.3 tl1.2 tl1.1 tl1.0 mnemonic: tl1 address: 8bh tl1.7-0: timer 1 low byte timer 0 msb bit: 7 6 5 4 3 2 1 0 th0.7 th0.6 th0.5 th0.4 th0.3 th0.2 th0.1 th0.0 mnemonic: th0 address: 8ch th0.7-0: timer 0 high byte
w78erd2/w78erd2a publication release date: february 14, 2007 - 13 - revision a10 timer 1 msb bit: 7 6 5 4 3 2 1 0 th1.7 th1.6 th1.5 th1.4 th1.3 th1.2 th1.1 th1.0 mnemonic: th1 address: 8dh th1.7-0: timer 1 high byte auxiliary register bit: 7 6 5 4 3 2 1 0 - - - - - - extram aleoff mnemonic: auxr address: 8eh bit name function 7~2 - reserve 1 extram 0 = enable aux-ram 1 = disable aux-ram 0 aleoff 0: ale expression is enabled. 1: ale expression is disabled. port 1 bit: 7 6 5 4 3 2 1 0 p1.7 p1.6 p1.5 p1.4 p1.3 p1.2 p1.1 p1.0 mnemonic: p1 address: 90h p1.7-0: general-purpose input/output port. port-r ead instructions read the port pins, while read- modify-write instructions read the port latch. port 4.1 low address comparator bit: 7 6 5 4 3 2 1 0 p41al.7 p41al.6 p 41al.5 p41al.4 p41al.3 p41a l.2 p41al.1 p41al.0 mnemonic: p41al address: 94h port 4.1 high address comparator bit: 7 6 5 4 3 2 1 0 p41ah.7 p41ah.6 p41ah.5 p41ah. 4 p41ah.3 p41ah.2 p41ah.1 p41ah.0 mnemonic: p41ah address: 95h
w78erd2/w78erd2a - 14 - serial port control bit: 7 6 5 4 3 2 1 0 sm0/fe sm1 sm2 ren tb8 rb8 ti ri mnemonic: scon address: 98h bit name function 7 sm0/fe serial port, mode 0 (sm0) bit or framing-e rror (fe) flag: the smod0 bit in pcon sfr determines whether this bit acts as sm0 or as fe. sm0 is described with smi1 below. when used as fe, this bit i ndicates whether the stop bit is invalid (fe=1) or valid (fe=0). this bit must be manually cleared by software. 6 sm1 serial port, mode 1 (sm1) bit: mode: sm0 sm1 description length baud rate 0 0 0 sy nchronous 8 6(6t mode)/12(12t mode) t clk 1 0 1 asynchronous 10 variable 2 1 0 asynch ronous 11 32/16(6t mode) or 64/32(12t mode) t clk 3 1 1 asynchronous 11 variable 5 sm2 multi-processor communication. (modes 2 and 3) set this bit to enable the multi-processor communication feature. with this feature, ri is not activated if the ninth data bit received (rb8) is 0. (mode 1) set this bit to 1 to keep ri de-acti vated if a valid stop bit is not received. (mode 0) sm2 controls the serial port clock. if clear, the serial port runs at 1/12 the oscillator. this is compatible with the standard 8052. 4 ren receive enable: 1 = serial reception is enabled 0 = serial reception is disabled 3 tb8 (modes 2 and 3) this is the ninth bit to be transmitted. this bit is set and cleared by software as desired. 2 rb8 (modes 2 and 3) this is the nint h data bit that was received. (mode 1) if sm2 is 0, rb8 is t he stop bit that was received. (mode 0) no function. 1 ti transmit interrupt flag: this flag is set by the hardware at the end of the eighth bit in mode 0 or at the beginning of the stop bit in modes 1 ? 3 during serial transmission. this bit must be cleared by software. 0 ri receive interrupt flag: this flag is set by the hardware at the end of the eighth bit in mode 0 or halfway through the stop bit in modes 1 ? 3 during serial reception. however, sm2 restricts this bit. this bit can be cleared only by software.
w78erd2/w78erd2a publication release date: february 14, 2007 - 15 - revision a10 serial data buffer bit: 7 6 5 4 3 2 1 0 sbuf.7 sbuf.6 sbuf.5 sbuf.4 sbuf.3 sbuf.2 sbuf.1 sbuf.0 mnemonic: sbuf address: 99h bit name function 7~0 sbuf serial port data is read from or written to this location. it actua lly consists of two separate, internal 8-bit registers, the re ceive register and the transmit buffer. any read access reads data from the receive regi ster, while write access writes to the transmit buffer. port 2 bit: 7 6 5 4 3 2 1 0 p2.7 p2.6 p2.5 p2.4 p2.3 p2.2 p2.1 p2.0 mnemonic: p2 address: a0h ram high byte address bit: 7 6 5 4 3 2 1 0 0 0 0 0 0 0 xramah.1 xramah.0 mnemonic: xramah address: a1h the aux-ram high byte address auxiliary 1 register bit: 7 6 5 4 3 2 1 0 - - - - gf2 0 - dps mnemonic: auxr1 address: a2h bit name function 7~4 - reserved 3 gf2 general purpose, user?defined flag. 2 0 the bit cannot be written and is always read as 0. 1 - reserved 0 dps 0 = switch to dptr0 1 = switch to dptr1
w78erd2/w78erd2a - 16 - watchdog timer reset register bit: 7 6 5 4 3 2 1 0 wdtrst.7 wdtrst.6 wdtrst.5 wdtrst.4 wdtrst.3 wdtrst.2 wdtrst.1 wdtrst.0 mnemonic: wdtrst address: a6h interrupt enable bit: 7 6 5 4 3 2 1 0 ea ec et2 es et1 ex1 et0 ex0 mnemonic: ie address: a8h bit name function 7 ea global interrupt enable. enable/disable all interrupts except for pfi. 6 ec enable pca interrupt. 5 et2 enable timer 2 interrupt. 4 es enable serial port interrupt. 3 et1 enable timer 1 interrupt. 2 ex1 enable external interrupt int1 . 1 et0 enable timer 0 interrupt. 0 ex0 enable external interrupt int0 . slave address bit: 7 6 5 4 3 2 1 0 mnemonic: saddr address: a9h bit name function 7~0 saddr the saddr should be programmed to the given or broadcast address for serial port to which the slave processor is designated. port 4.2 low address comparator bit: 7 6 5 4 3 2 1 0 p42al.7 p42al.6 p 42al.5 p42al.4 p42al.3 p42a l.2 p42al.1 p42al.0 mnemonic: p42al address: ach
w78erd2/w78erd2a publication release date: february 14, 2007 - 17 - revision a10 port 4.2 high address comparator bit: 7 6 5 4 3 2 1 0 p42ah.7 p42ah.6 p42ah.5 p42ah. 4 p42ah.3 p42ah.2 p42ah.1 p42ah.0 mnemonic: p42ah address: adh port 4 cs sign bit: 7 6 5 4 3 2 1 0 p4csin.7 p4csin.6 p4cs in.5 p4csin.4 p4csin.3 p4cs in.2 p4csin.1 p4csin.0 mnemonic: p4csin address: aeh port 3 bit: 7 6 5 4 3 2 1 0 p3.7 p32.6 p3.5 p32.4 p3.3 p3.2 p3.1 p3.0 mnemonic: p3 address: b0h port 4.3 low address comparator bit: 7 6 5 4 3 2 1 0 p43al.7 p43al.6 p 43al.5 p43al.4 p43al.3 p43a l.2 p43al.1 p43al.0 mnemonic: p43al address: b4h port 4.3 high address comparator bit: 7 6 5 4 3 2 1 0 p43ah.7 p43ah.6 p43ah.5 p43ah. 4 p43ah.3 p43ah.2 p43ah.1 p43ah.0 mnemonic: p43ah address: b5h interrupt priority high bit: 7 6 5 4 3 2 1 0 - ppch pt2h psh pt1h px1h pt0h px0h mnemonic: iph address: b8h bit name function 7 - this bit is not implemented and is always read high. 6 ppch 1: set the priority of the pca interrupt to the highest level. 5 pt2h 1: set the priority of the timer 2 interrupt to the highest level. 4 psh 1: set the priority of the serial port interrupt to the highest level. 3 pt1h 1: set the priority of the timer 1 interrupt to the highest level. 2 px1h 1: set the priority of external interrupt int1 to the highest level. 1 pt0h 1: set the priority of the timer 0 interrupt to the highest level. 0 px0h 1: set the priority of external interrupt int0 to the highest level.
w78erd2/w78erd2a - 18 - interrupt priority bit: 7 6 5 4 3 2 1 0 - ppc pt2 ps pt1 px1 pt0 px0 mnemonic: ip address: b8h bit name function 7 - this bit is not implemented and is always read high. 6 ppc 1: set the priority of the pca interrupt one level higher. 5 pt2 1: set the priority of the timer 2 interrupt one level higher. 4 ps 1: set the priority of the serial port interrupt one level higher. 3 pt1 1: set the priority of the timer 1 interrupt one level higher. 2 px1 1: set the priority of external interrupt int1 one level higher. 1 pt0 1: set the priority of the timer 0 interrupt one level higher. 0 px0 1: set the priority of external interrupt int0 one level higher. slave address mask enable bit: 7 6 5 4 3 2 1 0 mnemonic: saden address: b9h bit name function 7~0 saden this register enables the automatic addre ss recognition feature of the serial port. when a bit in saden is set to 1, the same bit in saddr is compared to the incoming serial data. when a bit in saden is set to 0, the same bit in saddr is a "don't care" value in the comparison. the se rial port interrupt occurs only if all the saddr bits where saden is set to 1 match the incoming serial data. on-chip programming control bit: 7 6 5 4 3 2 1 0 swrst/ reboot - - - - 0 fbootsl fprogen mnemonic: chpcon address: bfh
w78erd2/w78erd2a publication release date: february 14, 2007 - 19 - revision a10 bit name function 7 w: swreset r: reboot when fbootsl and fprogen are set to 1, set this bit to 1 to force the microcontroller to reset to the initia l condition, just like power-on reset. this action re-boots the microcontro ller and starts normal operation. read this bit to determine whether or not a hardware reboot is in progress. 6 ? 2 - reserved 1 fbootsl program location selection. this bit should be set before entering isp mode. 0: the loader program is in the 64-kb ap flash eprom. the 4-kb ld flash eprom is the destination for re-programming. 1: the loader program is in the 4-kb memory bank. the 64-kb ap flash eprom is the destination for re-programming. 0 fprogen flash eprom programming enable. 1: enable in-system programming mode. in this mode, erase, program and read operations are achieved duri ng device enters idle state. 0: disable in-system programming m ode. the on-chip flash memory is read-only. chpcon has an unrestricted read access, however, t he write access is protected by timed-access protection. see the section of timed-a ccess protection for more information. external interrupt control bit: 7 6 5 4 3 2 1 0 px3 ex3 ie3 it3 px2 ex2 ie2 it2 mnemonic: xicon address: c0h bit name function 7 px3 1: set the priority of external interrupt int3 one level higher. 6 ex3 1: enable external interrupt int3 . 5 ie3 interrupt int3 flag. this bit is set and clear ed automatically by the hardware when the interrupt is detected and processed. 4 it3 1: int3 is falling-edge triggered 0: int3 is low-level triggered 3 px2 1: set the priority of external interrupt int2 one level higher. 2 ex2 1: enable external interrupt int2 . 1 ie2 interrupt int2 flag. this bit is set and clear ed automatically by the hardware when the interrupt is detected and processed. 0 it2 1: int2 is falling-edge triggered 0: int2 is low-level triggered
w78erd2/w78erd2a - 20 - external interrupt high control bit: 7 6 5 4 3 2 1 0 pxh3 - - - pxh2 - - - mnemonic: xicon address: c1h bit name function 7 pxh3 1: set the priority of external interrupt int3 to the highest level. 6 - 4 - reserved 3 pxh2 1: set the priority of external interrupt int2 to the highest level. 2 - 0 - reserved port 4 control register a bit: 7 6 5 4 3 2 1 0 p41fun1 p41fun0 p41cmp1 p41cmp0 p40fun1 p40fun0 p40cmp1 p40cmp0 mnemonic: p4cona address: c2h bit name function 7, 6 p41fun1 p41fun0 p4.1 function control bits, similar to p43fun1 and p43fun0 below. 5, 4 p41cmp1 p41cmp0 p4.1 address-comparator length control bits, similar to p43cmp1 and p43cmp0 below. 3, 2 p40fun1 p40fun0 p4.0 function control bits, similar to p43fun1 and p43fun0 below. 1, 0 p40cmp1 p40cmp0 p4.0 address-comparator length control bits, similar to p43cmp1 and p43cmp0 below. port 4 control register b bit: 7 6 5 4 3 2 1 0 p43fun1 p43fun0 p43cmp1 p43cmp0 p42fun1 p42fun0 p42cmp1 p42cmp0 mnemonic: p4conb address: c3h
w78erd2/w78erd2a publication release date: february 14, 2007 - 21 - revision a10 bit name function 7, 6 p43fun1 p43fun0 00: mode 0. p4.3 is a general purpose i/o port, like port 1. 01: mode 1. p4.3 is a read-strobe signal for chip-select purposes. the address range depends on sfr p43a h, p43al, p43cmp1 and p43cmp0. 10: mode 2. p4.3 is a write-strobe signal for chip-select purposes. the address range depends on sfr p43a h, p43al, p43cmp1 and p43cmp0. 11: mode 3. p4.3 is a read/write-str obe signal for chip-select purposes. the address range depends on sfr p43a h, p43al, p43cmp1, and p43cmp0. 5, 4 p43cmp1 p43cmp0 chip-select signal address comparison: 00: compare the full 16-bit addr ess with p43ah and p43al. 01: compare the 15 msb of the 16- bit address with p43ah and p43al. 10: compare the 14 msb of the 16- bit address with p43ah and p43al. 11: compare the 8 msb of the 16-bit address with p43ah. 3, 2 p42fun1 p42fun0 p4.2 function control bits, similar to p43fun1 and p43fun0 above. 1, 0 p42cmp1 p42cmp0 p4.2 address-comparator length control bits, similar to p43cmp1 and p43cmp0 above. f/w flash low address bit: 7 6 5 4 3 2 1 0 mnemonic: sfral address: c4h f/w flash low byte address f/w flash high address bit: 7 6 5 4 3 2 1 0 mnemonic: sfrah address: c5h f/w flash high byte address f/w flash data bit: 7 6 5 4 3 2 1 0 mnemonic: sfrfd address: c6h f/w flash data
w78erd2/w78erd2a - 22 - f/w flash control bit: 7 6 5 4 3 2 1 0 0 wfwin oen cen ctrl3 ctrl2 ctrl1 ctrl0 mnemonic: sfrcn address: c7h bit name function 7 - reserved 6 wfwin on-chip flash eprom bank select fo r in-system programming. this bit should be defined by the loader program in isp mode. 0: 64-kb flash eprom is the destination for re-programming. 1: 4-kb flash eprom is the destination for re-programming. 5 oen flash eprom output enable. 4 cen flash eprom chip enable. 3 - 0 ctrl[3:0] flash control signals timer 2 control bit: 7 6 5 4 3 2 1 0 tf2 exf2 rclk tclk exen2 tr2 c/t2 cp/rl2 mnemonic: t2con address: c8h bit name function 7 tf2 timer 2 overflow flag: if rclk and tclk are 0, this bit is set when timer 2 overflows or when the count is equal to the value in the capture register in down-count mode. this bit can also be set by software, and it can only be cleared by software. 6 exf2 timer 2 external flag: when timer 2 is in either capture or auto-reload mode and dcen is 0, a negative transition on the t2ex pin (p1.1) and exen2=1 sets this flag. this flag can also be set by software. once set, this flag generates a timer-2 interrupt, if enabled, and it must be cleared by software. 5 rclk receive clock flag: set this bit to force timer 2 into baud-rate generator mode when receiving data on the serial port in modes 1 or 3. 1 = timer 2 overflow is the time base. 0 = timer 1 overflow is the time base. 4 tclk transmit clock flag: set this bit to force timer 2 into baud-rate generator mode when transmitting data on the serial port in modes 1 or 3. 1 = timer 2 overflow is the time base. 0 = timer 1 overflow is the time base.
w78erd2/w78erd2a publication release date: february 14, 2007 - 23 - revision a10 continued bit name function 3 exen2 timer 2 external enable: if timer 2 is not in baud-rate generator mode (see rclk and tclk above), set this bit to allow a negative transition on the t2ex pin to capture/reload timer 2 counter. 2 tr2 timer 2 run control: 1 = enable timer 2. 0 = disable timer 2, which preserves the current value in th2 and tl2. 1 c/t2 counter/timer select: 0 = timer 2 operates as a timer at a speed controlled by t2m (ckcon.5) 1 = timer 2 counts negative edges on the t2ex pin. 0 cp/rl2 capture/reload select: if exen2 is set to 1, this bit determines whether the capture or auto-reload function is activated. 0 = auto-reload when timer 2 overflows or a falling edge is detected on t2ex 1 = capture each falling edge is detected on t2ex if either rclk or tclk is set, this bit has no function, as timer 2 runs in auto- reload mode. timer 2 mode bit: 7 6 5 4 3 2 1 0 - - - - - - t2oe dcen mnemonic: t2mod address: c9h bit name function 7~2 - reserved 1 t2oe timer 2 output enable. this bit enabl es/disables the timer 2 clock-out function. 0 dcen down count enable: setting dcen to 1 allo ws t2ex pin to control the direction that timer 2 counts in 16-bit auto-reload mode. timer 2 capture low bit: 7 6 5 4 3 2 1 0 rcap2l.7 rcap2l.6 rcap2l.5 rcap2l.4 rcap2l.3 rcap2l.2 rcap2l.1 rcap2l.0 mnemonic: rcap2l address: cah rcap2l timer 2 capture lsb: in capture mode, rc ap2l is used to capture the tl2 value. in auto- reload mode, rcap2l is used as the lsb of the 16-bit reload value.
w78erd2/w78erd2a - 24 - timer 2 capture high bit: 7 6 5 4 3 2 1 0 rcap2h.7 rcap2h.6 rcap2h.5 rcap2h.4 rcap2h.3 rcap2h.2 rcap2h.1 rcap2h.0 mnemonic: rcap2h address: cbh rcap2h timer 2 capture hsb: in capture mode, rc ap2h is used to capture the th2 value. in auto- reload mode, rcap2h is used as the msb of the 16-bit reload value. timer 2 register low bit: 7 6 5 4 3 2 1 0 tl2.7 tl2.6 tlh2.5 tl2.4 tl2.3 tl2.2 tl2.1 tl2.0 mnemonic: tl2 address: cch tl2 timer 2 lsb timer 2 register high bit: 7 6 5 4 3 2 1 0 th2.7 th2.6 th2.5 th2.4 th2.3 th2.2 th2.1 th2.0 mnemonic: th2 address: cdh tl2 timer 2 msb program status word bit: 7 6 5 4 3 2 1 0 cy ac f0 rs1 rs0 ov f1 p mnemonic: psw address: d0h bit name function 7 cy carry flag: set when an arithmetic operati on results in a carry being generated from the alu. it is also used as the accumulator for bit operations. 6 ac auxiliary carry: set when the previous oper ation resulted in a carry from the high order nibble. 5 f0 general?purpose, user-defined flag 0. 4 rs1 register bank select bits: see below. 3 rs0 register bank select bits: see below. 2 ov overflow flag: set when a carry was generated from the seventh bit but not from the eighth bit as a result of the pr evious operation, or vice-versa. 1 f1 general?purpose, user-defined flag 1. 0 p parity flag: set and cleared by the hardware to indicate an odd or even number, respectively, of 1's in the accumulator.
w78erd2/w78erd2a publication release date: february 14, 2007 - 25 - revision a10 rs.1-0: register bank select bits: rs1 rs0 register bank address 0 0 0 00-07h 0 1 1 08-0fh 1 0 2 10-17h 1 1 3 18-1fh pca counter control register bit: 7 6 5 4 3 2 1 0 cf cr - ccf4 ccf3 ccf2 ccf1 ccf0 mnemonic: ccon address: d8h pca counter mode register bit: 7 6 5 4 3 2 1 0 cidl wdte - - - cps1 cps0 ecf mnemonic: cmod address: d9h pca module 0 register bit: 7 6 5 4 3 2 1 0 - ecom0 capp0 capn0 mat0 tog0 pwm0 eccf0 mnemonic: ccapm0 address: dah pca module 1 register bit: 7 6 5 4 3 2 1 0 - ecom1 capp1 capn1 mat1 tog1 pwm1 eccf1 mnemonic: ccapm1 address: dbh pca module 2 register bit: 7 6 5 4 3 2 1 0 - ecom2 capp2 capn2 mat2 tog2 pwm2 eccf2 mnemonic: ccapm2 address: dch pca module 3 register bit: 7 6 5 4 3 2 1 0 - ecom3 capp3 capn3 mat3 tog3 pwm3 eccf3 mnemonic: ccapm3 address: ddh
w78erd2/w78erd2a - 26 - pca module 4 register bit: 7 6 5 4 3 2 1 0 - ecom4 capp4 capn4 mat4 tog4 pwm4 eccf4 mnemonic: ccapm4 address: deh clock control register bit: 7 6 5 4 3 2 1 0 - - t2m t1m t0m - - md mnemonic: ckcon address: dfh bit name function 7 - reserved 6 - reserved 5 t2m timer 2 clock select: 0 = divide-by-6 clock 1 = divide-by-12 clock this bit has no effect if option bit 3 is set to 1 to select 12 clocks / machine cycle. 4 t1m timer 1 clock select: 0 = divide-by-6 clock 1 = divide-by-12 clock this bit has no effect if option bit 3 is set to 1 to select 12 clocks / machine cycle. 3 t0m timer 0 clock select: 0 = divide-by-6 clock 1 = divide-by-12 clock this bit has no effect if option bit 3 is set to 1 to select 12 clocks / machine cycle. 2 - reserved 1 - reserved 0 md stretch movx select bits: this bit is used to select the stretch value for the movx instruction, which enables the microcontrolle r to access slower memory devices or peripherals transparently and without the need for external circuits. the rd or wr strobe and all internal timings are stretc hed by the selected interval. the default value is 1 cycle. for faster access, set the value to 0. ckcon has an unrestricted read access, however, t he write access is protected by timed-access protection. see the section of timed-a ccess protection for more information.
w78erd2/w78erd2a publication release date: february 14, 2007 - 27 - revision a10 accumulator bit: 7 6 5 4 3 2 1 0 acc.7 acc.6 acc.5 acc. 4 acc.3 acc.2 acc.1 acc.0 mnemonic: acc address: e0h acc.7-0: the a (or acc) regist er is the standard 8052 accumulator. port 4 bit: 7 6 5 4 3 2 1 0 - - - - p4.3/int2 p4 .2/int3 p4.1 p4.0 mnemonic: acc address: e8h p4.3-0: port 4 is a bi-directional i/o port with internal pull-ups. bit name function 7 ? 4 - reserved 3 p4.3 port 4 data bit which outputs to pin p4.3 in mode 0, or external interrupt int2 . 2 p4.2 port 4 data bit which outputs to pin p4.2 in mode 0, or external interrupt int3 . 1 p4.1 port 4 data bit which outputs to pin p4.1 in mode 0. 0 p4.0 port 4 data bit which outputs to pin p4.0 in mode 0. pca counter low register bit: 7 6 5 4 3 2 1 0 cl.7 cl.6 cl.6 cl.4 cl.3 cl.2 cl.1 cl.0 mnemonic: cl address: e9h pca module 0 compare/capture low register bit: 7 6 5 4 3 2 1 0 ccap0l.7 ccap0l.6 ccap0l.5 ccap0l.4 ccap0l.3 ccap0l.2 ccap0l.1 ccap0l.0 mnemonic: ccap0l address: eah pca module 1 compare/capture low register bit: 7 6 5 4 3 2 1 0 ccap1l.7 ccap1l.6 ccap1l.5 ccap1l.4 ccap1l.3 ccap1l.2 ccap1l.1 ccap1l.0 mnemonic: ccap1l address: ebh
w78erd2/w78erd2a - 28 - pca module 2 compare/capture low register bit: 7 6 5 4 3 2 1 0 ccap2l.7 ccap2l.6 ccap2l.5 ccap2l.4 ccap2l.3 ccap2l.2 ccap2l.1 ccap2l.0 mnemonic: ccap2l address: ech pca module 3 compare/capture low register bit: 7 6 5 4 3 2 1 0 ccap3l.7 ccap3l.6 ccap3l.5 ccap3l.4 ccap3l.3 ccap3l.2 ccap3l.1 ccap3l.0 mnemonic: ccap3l address: edh pca module 4 compare/capture low register bit: 7 6 5 4 3 2 1 0 ccap4l.7 ccap4l.6 ccap4l.5 ccap4l.4 ccap4l.3 ccap4l.2 ccap4l.1 ccap4l.0 mnemonic: ccap4l address: eeh b register bit: 7 6 5 4 3 2 1 0 b.7 b.6 b.5 b.4 b.3 b.2 b.1 b.0 mnemonic: b address: f0h b.7-0: the b register is the standard 8052 regist er that serves as a second accumulator. chip enable register bit: 7 6 5 4 3 2 1 0 mnemonic: chpenr address: f6h pca counter high register bit: 7 6 5 4 3 2 1 0 ch.7 ch.6 ch.6 ch.4 ch.3 ch.2 ch.1 ch.0 mnemonic: ch address: f9h pca module 0 compare/capture high register bit: 7 6 5 4 3 2 1 0 ccap0h.7ccap0h.6 ccap0h.5ccap0h.4ccap0h.3ccap0h.2ccap0h.1 ccap0h.0 mnemonic: ccap0h address: fah
w78erd2/w78erd2a publication release date: february 14, 2007 - 29 - revision a10 pca module 1 compare/capture high register bit: 7 6 5 4 3 2 1 0 ccap1h.7ccap1h.6 ccap1h.5ccap1h.4ccap1h.3ccap1h.2ccap1h.1 ccap1h.0 mnemonic: ccap1h address: fbh pca module 2 compare/capture high register bit: 7 6 5 4 3 2 1 0 ccap2h.7ccap2h.6 ccap2h.5ccap2h.4ccap2h.3ccap2h.2ccap2h.1 ccap2h.0 mnemonic: ccap2h address: fch pca module 3 compare/capture high register bit: 7 6 5 4 3 2 1 0 ccap3h.7ccap3h.6 ccap3h.5ccap3h.4ccap3h.3ccap3h.2ccap3h.1 ccap3h.0 mnemonic: ccap3h address: fdh pca module 4 compare/capture high register bit: 7 6 5 4 3 2 1 0 ccap4h.7 ccap4h.6 ccap4h.5 ccap4h.4 ccap4h.3 ccap4h.2 ccap4h.1 ccap4h.0 mnemonic: ccap4h address: feh
w78erd2/w78erd2a - 30 - 7. port 4 and base address registers port 4, address e8h, is a 4-bit, multi-purpose, programmable i/o port. each bit can be configured individually, and registers p4cona and p4conb contain the control bits that select the mode of each pin. each pin has four operating modes. mode 0: bi-directional i/o port, like port 1. p4 .2 and p4.3 serve as external interrupts int3 and int2 , if enabled. mode 1: read-strobe signals synchronized with the rd signal at specified addresses. these signals can be used as chip-select signals for external peripherals. mode 2: write-strobe signals synchronized with the wr signal at specified addresses. these signals can be used as chip-select signals for external peripherals. mode 3: read/write-strobe si gnals synchronized with the rd or wr signal at specified addresses. these signals can be used as chip-select signals for external peripherals. in modes 1 ? 3, the address range for chip-selec t signals depends on the content s of registers p4xah and p4xal, which contain the high-order byte and lo w-order byte, respectively, of the 16-bit address comparator for p4.x. this is illu strated in the following schematic. address bus bit length selectable comparator register p4xal p4xah equal p4.x mux 4->1 p4 register p4.x read write data i/o rd_cs wr_cs rd/wr_cs p4xcmp0 p4xcmp1 p4xfun0 p4xfun1 p4xcsinv p4.x input data bus register pin figure 7-1 for example, the following program sets up p4.0 as a write-strobe signal for i/o port addresses 1234h ? 1237h with positive polarity, while p4.1 ? p4.3 are used as general i/o ports.
w78erd2/w78erd2a publication release date: february 14, 2007 - 31 - revision a10 mov p40ah, #12h mov p40al, #34h ; base i/o address 1234h for p4.0 mov p4cona, #00001010b ; p4.0 is a write-strobe signal; address lines a0 and a1 are masked. mov p4conb, #00h ; p4.1 ? p4.3 are general i/o ports mov p2econ, #10h ; set p40sinv to 1 to invert the p4.0 write-strobe to positive polarity. then, any instruction movx @dptr, a (where dptr is in 1234h ? 1237h) generates a positive- polarity, write-strobe signal on pin p4.0, while the instruction mov p4, #xx puts bits 3 ? 1 of data #xx on pins p4.3 ? p4.1.
w78erd2/w78erd2a - 32 - 8. interrupts this section provides more information about external interrupts int2 and int3 and provides an overview of interrupt priori ty levels and polling sequences. 8.1 external interrupts 2 and 3 the w78erd2 offers two additional external interrupts, int2 and int3 , similar to external interrupts int0 and int1 in the standard 80c52. these interrupts are configured by the xicon (external interrupt control) register, which is not a standard register in the 80c52. its address is 0c0h. xicon is bit-addressable; for example, "set b 0c2h" sets the ex2 bit of xicon. 8.2 interrupt priority each interrupt has one of four priority levels in the w78erd2, as shown below. four-level interrupt priority priority bits iph.x ip.x interrupt priority level 0 0 level 0 (lowest priority) 0 1 level 1 1 0 level 2 1 1 level 3 (highest priority) interrupts with the same priority level are polled in the sequence indicated below. nine-source interrupt information interrupt source polling sequence within priority level enable required settings interrupt type edge/level vector address external interrupt 0 0 (highest) ie.0 tcon.0 03h timer/counter 0 1 ie.1 - 0bh external interrupt 1 2 ie.2 tcon.2 13h timer/counter 1 3 ie.3 - 1bh programmable counter array 4 ie.6 - 33h serial port 5 ie.4 - 23h timer/counter 2 6 ie.5 - 2bh external interrupt 2 7 xicon.2 xicon.0 3bh external interrupt 3 8 (lowest) xicon.6 xicon.3 43h
w78erd2/w78erd2a publication release date: february 14, 2007 - 33 - revision a10 9. programmable timers/counters the w78erd2 has three 16-bit programmable timer/counters. time-base selection the w78erd2 offers two speeds for the timer. the ti mers can count at 1/12 of the clock, the same speed they have in the standard 8051 fam ily. alternatively, the timers c an count at 1/6 of the clock, called turbo mode. the speed is controlled by bits t0m, t1m and t2m bits in ckcon. the default value is zero, which selects 1/12 of the clock. these 3 bits, t0m, t1m and t2m, have no effect if option bit 3 is set to 1 to select 12 clocks / machine cycle. 9.1 timer 0 and timer 1 timers 0 and 1 each have a 16-bit timer/counter which consists of two eight-bit registers: timer 0 consists of th0 (8 msb) and tl0 (8 l sb), and timer 1 consists of th1 and tl1. these timers/counters can be configured to operate either as timers, machine?cycle counters or counters based on external inputs. the "timer" or "counter" function itself is selected by the corresponding " t c/ " bit in the tmod register: bit 2 for timer 0 and bit 6 for timer 1. in addition, each timer/counter can operate in one of four possible modes, which are selected by bits m0 and m1 in tmod. the rest of this section explains the time- base for the timers and then introduces each mode. mode 0 in mode 0, the timer/counter is a 13-bit counter w hose eight msb are in thx and five lsb are the five lower bits in tlx. the upper three bits in tlx are ignored. because thx and tlx are read separately, the timer/counter acts like an eight-bit count er with a five-bit, divide-by-32 pre-scale. counting is enabled only when trx is set and either gate = 0 or intx = 1. what the timer/counter counts depends on t c/ . when t c/ is set to 0, the timer/count er counts the negative edges of the clock according to the time-base selected by bits txm in ckcon. when t c/ is set to 1, it counts falling edges on t0 (p3.4, for timer 0) or t1 (p3. 5, for timer 1). when the 13-bit counter reaches 1fffh, the next count rolls over the timer/counter to 0000h, and the timer overflow flag tfx (in tcon) is set. if enabled, an interrupt occurs.
w78erd2/w78erd2a - 34 - 1/6 1/12 c/t = tmod.2 (c/t = tmod.6) t0m = ckcon.3 (t1m = ckcon.4) m1,m0 = tmod.1,tmod.0 (m1,m0 = tmod.5,tmod.4) interrupt t0 = p3.4 (t1 = p3.5) th0 (th1) tl0 (tl1) tf0 (tf1) tr0 = tcon.4 (tr1 = tcon.6) gate = tmod.3 (gate = tmod.7) int0 = p3.2 (int1 = p3.3) 7 0 tfx 4 7 0 timer 1 functions are shown in brackets 1 00 0 0 1 01 osc figure 9-1 timer/counter mode 0 & mode 1 mode 1 mode 1 is similar to mode 0, except that the time r/counter is 16-bit counter , not a 13-bit counter. all the bits in thx and tlx are used. roll-over o ccurs when the timer moves from ffffh to 0000h. mode 2 mode 2 is similar to mode 0, except that tlx ac ts like an eight-bit counter and thx holds the auto- reload value for tlx. when the tlx register overflow s from ffh to 00h, the timer overflow flag tfx bit (in tcon) is set, tlx is reloaded with the content s of thx, and the counting process continues. the reload operation does not affect the thx register. 1/6 1/12 t0m = ckcon.3 (t1m = ckcon.4) c/t = tmod.2 (c/t = tmod.6) interrupt t0 = p3.4 (t1 = p3.5) th0 (th1) tl0 (tl1) tf0 (tf1) tr0 = tcon.4 (tr1 = tcon.6) gate = tmod.3 (gate = tmod.7) int0 = p3.2 (int1 = p3.3) 7 0 tfx 7 0 timer 1 functions are shown in brackets 1 0 0 1 osc figure 9-2 timer/counter mode 2
w78erd2/w78erd2a publication release date: february 14, 2007 - 35 - revision a10 mode 3 mode 3 is used when an extra eight-bit timer is needed, and it has different effects on timer 0 and timer 1. timer 0 separates tl0 and th0 into two separate ei ght-bit count registers. tl0 uses the timer 0 control bits t c/ , gate, tr0, int0 and tf0 and can count clock cycles (clock / 12 or clock / 6) or falling edges on pin t0. meanwhile, th0 takes over tr1 and tf1 from timer 1 and can count clock cycles (clock / 12 or clock / 6). mode 3 simply freezes timer 1, which provides a wa y to turn it on and off. when timer 0 is in mode 3, timer 1 can still be used in modes 0, 1 and 2, but its flexibility is limited. timer 1 can still be used as a timer / counter (or a baud-rate generator for the serial port) and retains the use of gate and int1 pin, but it no longer has control over the overflow flag tf1 and enable bit tr1. 1/6 1/12 t0m = ckcon.3 interrupt c/t = tmod.2 t0 = p3.4 th0 tl0 tr0 = tcon.4 gate = tmod.3 tr1 = tcon.6 int0 = p3.2 7 0 tf1 7 0 interrupt tf0 1 0 0 1 osc figure 9-3 timer/counter 0 mode 3 9.2 timer/counter 2 timer 2 is a 16-bit up/down counter equipped with a c apture/reload capability. it is configured by the t2mod register and controlled by the t2con regist er. as with timers 0 and 1, timer 2 can count clock cycles (fosc / 12 or fosc / 6) or the external t2 pin, as selected by t2 c/ , and there are four operating modes, each discussed below. capture mode capture mode is enabled by setting the rl2 cp/ bit in the t2con register. in capture mode, timer 2 serves as a 16-bit up-counter. when the counter ro lls over from ffffh to 0000h, the tf2 bit is set, and, if enabled, an interrupt is generated. if the exen2 bit is set, then a negative transition on the t2ex pin captures the value in tl2 and th2 registers in the rcap2l and rcap2h registers. this action also causes the exf2 bit in t2con to be set, which may also generate an interrupt.
w78erd2/w78erd2a - 36 - rclk+tclk=0, rl2 cp/ =t2con.0=1 1/6 1/12 t2m = ckcon.5 c/t2 = t2con.1 t2con.7 t2 = p1.0 t2con.6 tr2 = t2con.2 t2ex = p1.1 exen2 = t2con.3 exf2 timer 2 interrupt tf2 th2 tl2 rcap2h rcap2l 1 0 0 1 osc figure 9-4 16-bit capture mode auto-reload mode, counting up this mode is enabled by clearing the rl2 cp/ bit in t2con and the dcen bit in t2mod. in this mode, timer 2 is a 16-bit up-counter. when the count er rolls over from ffffh to 0000h, the contents of rcap2l and rcap2h are automatically reloaded into tl2 and th2, and the timer overflow bit tf2 is set. if the exen2 bit is set, then a negative transiti on of t2ex pin also causes a reload, which also sets the exf2 bit in t2con. rclk+tclk=0, rl2 cp/ =t2con.0=0, dcen=0 1/6 1/12 t2m = ckcon.5 c/t2 = t2con.1 t2con.7 t2 = p1.0 t2con.6 tr2 = t2con.2 t2ex = p1.1 exen2 = t2con.3 exf2 timer 2 interrupt tf2 th2 tl2 rcap2 h rcap2l 1 0 0 1 osc figure 9-5 16-bit auto-reload mode, counting up auto-reload mode, counting up/down this mode is enabled when the rl2 cp/ bit in t2con is clear and the dcen bit in t2mod is set. in this mode, timer 2 is an up/down-counter whose dire ction is controlled by the t2ex pin (1 = up, 0 = down). when timer 2 overflows while counting up, the counter is reloaded by rcap2l and rcap2h. when timer 2 is counting down, the counter is reloaded with ffffh when timer 2 is equal to rcap2l and rcap2h. in either case, the timer over flow bit tf2 is set, and the exf2 bit is toggled, though exf2 can not generate an interrupt in this mode.
w78erd2/w78erd2a publication release date: february 14, 2007 - 37 - revision a10 rclk+tclk=0, rl2 cp/ =t2con.0=0, dcen=1 c/t = t2con.1 1/6 1/12 t2m = ckcon.5 down counting reload value t2con.7 up counting reload value t2 = p1.0 t2con.6 tr2 = t2con.2 t2ex = p1.1 exf2 timer 2 interrupt tf2 th2 tl2 rcap2h rcap2l 1 0 0 1 0ffh 0ffh osc figure 9-6 16-bit auto-reload up/down counter baud rate generator mode baud-rate generator mode is enabled by setting either the rclk or tclk bits in t2con register. in baud-rate generator mode, timer 2 is a 16-bit up-counter that automatically rel oads when it overflows, but this overflow does not set the timer overflow bit tf2. if exen2 is set, then a negative transition on the t2ex pin sets exf2 bit in t2con and, if enabled, generates an interrupt request. rclk+tclk=1 c/t = t2con.1 t2 = p1.0 t2con.6 tr2 = t2con.2 t2ex = p1.1 exen2 = t2con.3 exf2 timer 2 overflow timer 2 interrupt th2 tl2 rcap2h rcap2l 0 1 osc figure 9-7 baud rate generator mode
w78erd2/w78erd2a - 38 - 10. enhanced full duplex serial port the w78erd2 serial port is a full-duplex port, and t he w78erd2 provides additional features such as frame-error detection and automatic address recognition. the serial port runs in one of four operating modes. serial ports modes sm1 sm0 mode type baud clock frame size start bit stop bit 9th bit function 0 0 0 synch. 12 tclks 8 bits no no none 0 1 1 asynch. timer 1 or 2 10 bits 1 1 none 1 0 2 asynch. 32 or 64 tclks 11 bits 1 1 0, 1 1 1 3 asynch. timer 1 or 2 11 bits 1 1 0, 1 in synchronous mode (mode 0), the w78erd2 generat es the clock and operates in a half-duplex mode. in asynchronous modes (modes 1 ? 3), full-duplex operation is available so that the serial port can simultaneously transmit and receive data. in any mode, register sbuf functions as both the transmit register and the receive buffer. any write to sbuf writes to the transmit register, while any read from sbuf reads from the receive buffer. the rest of this section discusses each operating mode and then discusses frame-error detecti on and automatic address recognition. 10.1 mode 0 mode 0 is a half-duplex, synchronous mode. rxd transmits and receives serial data, and txd transmits the shift clock. the txd clock is prov ided by the w78erd2. eight bits are transmitted or received per frame, lsb first. the baud rate is fix ed at 1/12 of the oscillator frequency. the functional block diagram is shown below. sbuf transmit shift register receive shift register tx shift parout internal data bus internal data bus rxd p3.0 alternate output function txd p3.1 alternate output function rxd p3.0 alternate iutput function serial port interrupt write to sbuf tx start sout ti ri ren parin load clock read sbuf sbuf tx clock ri serial controlle shift clock rx clock load sbuf rx start rx shift clock sin 12 osc figure 10-1 serial port mode 0
w78erd2/w78erd2a publication release date: february 14, 2007 - 39 - revision a10 as mentioned before, data enters and leaves the serial port on rxd. txd line provides the shift clock, which shifts data into and out of the w78erd2 and the device at the other end of the line. any instruction that writes to sbuf starts the transmi ssion. the shift clock is activated, and the data is shifted out on the rxd pin until all eight bits are transmitted. if sm2 is set to 1, the data appears on rxd one clock period before the falling edge on txd, and the txd clock then remains low for two clock periods before going high again. if sm2 is set to 0, the data appears on rxd three clock periods before the falling edge on txd, and the txd clock then remains low for six clock periods before going high again. this ensures that the receiving devic e can clock rxd data on the rising edge of txd or when the txd clock is low. finally, the ti flag is set high in c1 once the last bit has been transmitted. the serial port receives data when ren is 1 and ri is zero. the txd clock is activated, and the serial port latches data on the rising edge of the shift clock. as a result, the external device should present data on the falling edge of txd. this process conti nues until all eight bits have been received. then, after the last rising edge on txd, the ri flag is set high in c1, which stops reception until ri is cleared by the software. 10.2 mode 1 mode 1 is a full?duplex, asynchronous mode. serial communication frames are made up of ten bits transmitted on txd and received on rxd. the ten bits c onsist of a start bit (0), eight data bits (lsb first), and a stop bit (1). when the w78erd2 receives data, the stop bit goes into rb8 in scon. the baud rate is either 1/16 or 1/32 of the timer 1 overfl ow, which can be set to a variety of reload values. (the 1/16 or 1/32 factor is determined by the smod bit in pcon sfr.) the functional diagram is shown below. sbuf rb8 transmit shift register receive shift register tx shift parout d8 internal data bus internal data bus txd rxd serial port interrupt smod = tclk rclk sample write to sbuf tx start sout 0 1 0 1 ti 1 0 parin stop start load clock read sbuf timer 2 overflow timer 1 overflow tx clock ri serial controller rx clock load sbuf rx start rx shift 2 16 1-to-0 detector bit detector 16 clock sin figure 10-2 serial port mode 1
w78erd2/w78erd2a - 40 - transmission begins when data is written to sbuf but is synchronized with the roll-over of timer 1 (divided by 16 or 32, as configured) and not the write signal. the w78erd2 waits until the next roll- over of timer 1 (divided by 16 or 32) before the data is put on txd. the next bit is placed on txd after the next rollover. after all eight bits of data are tr ansmitted, the stop bit is transmitted. finally, the ti flag is set, at the tenth rollover after the write signal. reception is enabled only if ren is high. the w78e rd2 samples the rxd line at a rate of 16 times the selected baud rate, looking for a falling edge. when a falling edge is detected on the rxd pin, timer 1 (divided by 16 or 32) is immediately reset to align the bit boundaries better, and the serial port starts receiving data. the 16 states of the counter effectively divide the time into 16 slices, and bit detection is done on a best-of-three basis using the ei ghth, ninth and tenth states. if the start bit is invalid (1), reception is aborted, and the serial port resumes looking for a falling edge on rxd. if the start bit is valid, the eight data bits are shifted in. then, if (1) ri = 0 and (2) sm2 = 0 or the stop bit = 1, the stop bit is put into rb8, the data is put in sbuf, and ri is set. otherwise, the received frame may be lost. in the middle of the stop bit, the w78erd2 resumes looking for falling edges on rxd. 10.3 mode 2 mode 2 is a full-duplex, asynchronous mode. serial communication frames are made up of eleven bits transmitted on txd and received on rxd. the eleven bits consist of a start bit (0), eight data bits (lsb first), a programmable ninth bit (tb8) and a stop bit (1). the ninth bit is read into and transmitted from rb8. the baud rate is either 1/32 or 1/64 of the oscillator frequency, and the 1/32 or 1/64 factor is determined by the smod bit in pcon sf r. the functional diagram is shown below. sbuf rb8 transmit shift register receive shift register tx shift parout d8 internal data bus internal data bus txd rxd serial port interrupt smod = sample write to sbuf tx start sout 0 1 ti parin stop start load clock read sbuf tx clock ri serial controller rx clock load sbuf rx start rx shift 2 16 1-to-0 detector bit detector 16 clock sin d8 tb8 1/2 fosc figure 10-3 serial port mode 2
w78erd2/w78erd2a publication release date: february 14, 2007 - 41 - revision a10 transmission begins when data is written to sbuf but is synchronized with the ro ll-over of the counter (divided by 32 or 64, as configured) and not the write signal. the w78erd2 waits until the next roll- over of the counter (divided by 32 or 64) before t he data is put on txd. the next bit is placed on txd after the next rollover. after all nine bits of data ar e transmitted, the stop bit is transmitted. finally, the ti flag is set, at the eleventh rollover after the write signal. reception is enabled only if ren is high. the w78e rd2 samples the rxd line at a rate of 16 times the selected baud rate, looking for a falling edge. w hen a falling edge is detected on the rxd pin, the counter (divided by 32 or 64) is immediately reset to align the bit boundaries better, and the serial port starts receiving data. the 16 states of the counter effectively divide the time into 16 slices, and bit detection is done on a best-of-three basis using the ei ghth, ninth and tenth states. if the start bit is invalid (1), reception is aborted, and the serial port resumes looking for a falling edge on rxd. if the start bit is valid, the rest of the bits are shifted in. then, if (1) ri = 0 and (2) either sm2 = 0 or the received 9th bit = 1, the ninth bit is put into rb8, the data is put in sbuf, and ri is set. otherwise, the received frame may be lost. in the middle of the stop bit, the w78erd2 resumes looking for falling edges on rxd. 10.4 mode 3 mode 3 is similar to mode 2 in all respects, except that the baud rate is programmable the same way it is programmable in mode 1. the f unctional diagram is shown below. sbuf rb8 transmit shift register receive shift register tx shift parout d8 internal data bus internal data bus txd rxd serial port interrupt smod = tclk rclk sample write to sbuf tx start sout 0 1 0 1 ti 1 0 parin stop start load clock read sbuf timer 2 overflow timer 1 overflow tx clock ri serial controller rx clock load sbuf rx start rx shift 2 16 1-to-0 detector bit detector 16 clock sin d8 tb8 figure 10-4 serial port mode 3
w78erd2/w78erd2a - 42 - 10.5 framing error detection a frame error occurs when a valid stop bit is not det ected. this could indicate incorrect serial data communication. typically, the frame error is due to noise or contention on the serial communication line. the w78erd2 has the ability to detect frami ng errors and set a flag which can be checked by software. the frame error fe bit is located in scon.7. th is bit is normally used as sm0 in the standard 8051 family. however, in the w78erd2 it serves a dual function and is called sm0/fe. there are actually two separate flags, one for sm0 and the other for fe. t he flag that is actually accessed as scon.7 is determined by smod0 (pcon.6) bit. when smod0 is set to 1, then the fe flag is accessed. when smod0 is set to 0, then the sm0 flag is accessed. the fe bit is set to 1 by the hardware but must be cleared by software. once fe is set, any frames received afterwards, even those without any errors , do not clear the fe flag. the flag has to be cleared by software. note that smod0 must be set to 1 while reading or writing to fe. 10.6 multi-processor communications multi-processor communication makes use of the 9t h data bit in modes 2 and 3. in the w78erd2, the ri flag is set only if the received byte corresponds to the given or broadcast address. this hardware feature eliminates the software overhead requir ed in checking every received address and greatly simplifies the software programmer task. in multi-processor communication mode, the address bytes are distinguished from the data bytes by the 9th bit, which is set high for address bytes. w hen the master processor wants to transmit a block of data to one of the slaves, it first sends out the addr ess of the target slave (o r slaves). all the slave processors should have their sm2 bit set high when waiting for an address byte. this ensures that they are interrupted only by the reception of an address byte. the automatic address recognition feature ensures that only the addressed slave is actually interrupted because the address comparison is done by the hardware, not the software. the addressed slave clears the sm2 bit, thereby clear ing the way to receive data bytes. with sm2 = 0, the slave is interrupted on the reception of ev ery single complete frame of data. the unaddressed slaves are not affected, as they are still waiting for their address. the master processor can selectively communicate wi th groups of slaves by using the given address. all the slaves can be addressed together using t he broadcast address. the addresses for each slave are defined in the saddr and saden registers. the sl ave address is an eight-bit value specified in the saddr sfr. the saden sfr is actually a mask fo r the byte value in saddr. if a bit position in saden is 0, then the corresponding bit position in saddr is don't care. only those bit positions in saddr whose corresponding bits in saden are 1 are used to obtain the given address. this gives the user flexibility to address multiple slav es without changing the slave address in saddr. the following example shows how the user can defi ne the given address to address different slaves.
w78erd2/w78erd2a publication release date: february 14, 2007 - 43 - revision a10 slave 1: saddr 1010 0100 saden 1111 1010 given 1010 0x0x slave 2: saddr 1010 0111 saden 1111 1001 given 1010 0xx1 the given address for slaves 1 and 2 differ in the lsb. for slave 1, it is a don't-care, while for slave 2 it is 1. thus to communicate only with slave 1, the master must send an address with lsb = 0 (1010 0000). similarly the bit 1 position is 0 for slave 1 and don't care for slave 2. hence to communicate only with slave 2 the master has to transmit an address with bit 1 = 1 (1010 0011). if the master wishes to communicate with both slaves simult aneously, then the address must have bit 0 = 1 and bit 1 = 0. the bit 3 position is don't-care for both the sl aves. this allows two different addresses to select both slaves (1010 0001 and 1010 0101). the master can communicate with all the slaves simultaneously with the broadcast address. this address is formed from the logical or of the sa ddr and saden sfrs. the zeros in the result are defined as don't cares. in most cases, the broadcas t address is ffh. in the previous example, the broadcast address is (1111111x) for slave 1 and (11111111) for slave 2. the saddr and saden sfrs are located at addresse s a9h and b9h, respectively. on reset, these registers are initialized to 00h. this results in given address and broadcast address being set as xxxx xxxx(i.e. all bits don't care). this effectiv ely removes the multi-processor communications feature, since any selectivity is disabled.
w78erd2/w78erd2a - 44 - 11. programmable counter array (pca) the pca is a special 16-bit timer that has five 16-bit capture/compare modules associated with it. each module can be programmed to operate in one of four modes: rising and/or falling edge capture, software timer, high-speed output, or pulse width modulator. each module has a pin associated with it in port 1. module 0 is connected to p1.3 (cex0), module 1 to p1.4 (cex1), and so on. pca timer/counter module0 module1 module2 module3 module4 p1.3/cex0 p1.4/cex1 p1.5/cex2 p1.6/cex3 p1.7/cex4 time base for pca modules module functions: 16-bit capture 16-bit timer/compare 16-bit high speed output 8-bit pwm watchdog timer (module 4 only) ch cl 16-bit up-counter figure 11-1 programmable counter array (pca) each module has a special function register ccapm n , where n is the same number as the module (ccapm0 for module0, ccapm1 for module1, etc.). ccapm n contains the bits that control the mode of each module. ccapmn: pca module compare/capture register ccapm0(dah) , ccapm1(dbh) , ccapm2(dch) , ccapm3(ddh), ccapm4(deh) bit name function 7 - reserved 6 ecomn enable comparator. ecomn = 1 enables the comparator function 5 cappn capture positive. cappn = 1 enables positive-edge capture. 4 capnn capture negative. capn n = 1 enables negative-edge capture. 3 matn match. when matn = 1 a match of the pca counter with this module?s compare/capture register causes the ccf n bit in ccon to be set and, if eccfn is set, generating an interrupt. 2 togn toggle. when togn = 1 a match of the pca counter with this module?s compare/capture register caus es the cexn bit to toggle. 1 pwmn pulse width modulation mode. pwmn = 1 enables the cexn bit to be used for pulse-width modulated output. 0 eccfn enable ccf interrupt. enables the compare/capture flag ccfn in the ccon register to generate an interrupt.
w78erd2/w78erd2a publication release date: february 14, 2007 - 45 - revision a10 module function ecomn cappn capnn matn togn pwmn eccfn no operation 0 0 0 0 0 0 0 16-bit capture by a positive edge trigger on cexn x 1 0 0 0 0 x 16-bit capture by a negative trigger on cexn x 0 1 0 0 0 x 16-bit capture by a transition on cexn x 1 1 0 0 0 x 16-bit software timer 1 0 0 1 0 0 x 16-bit high speed output 1 0 0 1 1 0 x 8-bit pwm 1 0 0 0 0 1 0 watchdog timer (only in module4) 1 0 0 1 x 0 x pca module modes (ccapmn register) pwm enables pulse width modulation. the tog bit causes the output cex n to toggle when there is a match between the pca counter and the module?s co mpare/capture register. the match bit mat causes the ccf bit in the ccon register to be set when there is a match between the pca counter and the module?s compare/capture register, and t he eccf bit enables the ccf flag to generate an interrupt. the bits capp and capn determine whet her positive and negative edges, respectively, are captured. the bit ecom enables the comparator function. the pca timer is the common time-base for all fi ve modules and can be programmed to select the appropriate timer source. the default value is 12 clocks (12t) per machine cycle, and 6t can also be selected by a bit in the options registers. the ac tual timer is then determined by the cps1 and cps2 bits in the cmod sfr, as follows: cps1 cps0 pca timer count source for 12t pca timer count source for 6t 0 0 oscillator frequency / 12 oscillator frequency / 6 0 1 oscillator frequency / 4 oscillator frequency / 2 1 0 timer 0 overflow timer 0 overflow 1 1 external input at eci pin external input at eci pin
w78erd2/w78erd2a - 46 - cmod(d9h): pca counter mode register bit name function 7 cild counter idle control: cild = 0 program s the pca counter to continue functioning in idle mode; cild = 1 programs it to stop in idle mode. 6 wdte watchdog timer enable: wdte = 0 disables the watchdog timer function in pca module 4. wdte = 1 enables it. 5 - reserved 4 - reserved 3 - reserved 2 cps1 pca count pulse select bit 1 1 cps0 pca count pulse select bit 0 0 ecf pca enable counter overflow interrupt: ecf = 1 enables cf bit in ccon to generate an interrupt. ecf = 0 disables the interrupt. there are three additional bits in the cmod sfr. cild allows the pca to stop during idle mode, wdte enables and disables the watchdog functi on executed in module 4, and ecf causes an interrupt when the pca timer overflows ( and the pca overflow flag cf is set). the ccon sfr contains the run-control bit for the pca and the flags for the pca timer overflow (cf) and each module match / capture (ccfn). ccon(d8h): pca counter control register bit name function 7 cf pca counter overflow flag. set by har dware when the counter rolls over. cf generates an interrupt if bit ecf in cm od is set. cf may be set by either hardware or software but can only be cleared by software. 6 cr pca counter run control bit. set by softw are to turn on the pca counter. must be cleared by software to turn the pca counter off. 5 - reserved 4 ccf4 pca module4 interrupt flag. set by hardw are when a match or capture occurs. must be cleared by software. 3 ccf3 pca module3 interrupt flag. set by hardw are when a match or capture occurs. must be cleared by software. 2 ccf2 pca module2 interrupt flag. set by hardw are when a match or capture occurs. must be cleared by software. 1 ccf1 pca module1 interrupt flag. set by hardw are when a match or capture occurs. must be cleared by software. 0 ccf0 pca module0 interrupt flag. set by hardw are when a match or capture occurs. must be cleared by software. the cr bit (ccon.6) must be set by the software, and the pca is turned off by clearing this bit. the cf bit (ccon.7) is set when the pca counter over flows, and an interrupt is generated if the ecf bit in the cmod register is set. the cf bit can only be cleared by software. ccon.0~ccon.4 are the
w78erd2/w78erd2a publication release date: february 14, 2007 - 47 - revision a10 flags for the modules and are set by hardware when ei ther a match or a capture occurs. these flags can only be cleared by software. the next five sections provide more information about each of the five modes (four modes for all registers and the watchdog timer in module 4). 11.1 pca capture mode to use one of the pca modules in capture mode, either one or both of the ccapm bits capn and capp for that module must be set. cf ccf0 ccf1 ccf2 ccf3 ccf4 - cr ccon(d8h) cexn ch cl ccapnh ccapnl - eccfn pwmn togn matn capnn cappn ecomn ccapmn, n=0~4 (dah~deh) pca timer/counter pca interrupt 0000 capture to ccfn figure 11-2 pca capture mode in capture mode, the external cex n input is sampled for a transition. when a valid transition occurs, the pca hardware loads the value of the pca count er registers ch and cl into the module?s capture registers (ccapnh and ccapnl). if the ccfn (cco n) and eccfn (ccapmn) bits are set, then an interrupt is generated. 11.2 16-bit software timer comparator mode the pca modules can be used as software timers by setting both the ecom and mat bits in the ccapmn register.
w78erd2/w78erd2a - 48 - cf ccf0 ccf1 ccf2 ccf3 ccf4 - cr ccon(d8h) - eccfn pwmn togn matn capnn cappn ecomn ccapmn, n=0~4 (dah~deh) 000 write to ccapnl write to ccapnh ccapnh ccapnl ch cl pca timer/counter 16-bit comparator enable pca interrupt to ccfn match 0 01 figure 11-3 pca 16-bit timer comparator mode in this mode, the pca timer is compared to the module?s capture registers. when a match occurs, an interrupt is generated if the ccfn (ccon) and eccfn (ccapmn) bits are set. 11.3 high speed output mode to activate this mode, the tog, mat, and ecom (ccapmn) bits must be set. cf ccf0 ccf1 ccf2 ccf3 ccf4 - cr ccon(d8h) - eccfn pwmn togn matn capnn cappn ecomn ccapmn, n=0~4 (dah~deh) 010 write to ccapnl write to ccapnh ccapnh ccapnl ch cl pca timer/counter 16-bit comparator enable pca interrupt to ccfn match 0 cexn 01 figure 11-4 pca high speed output mode in this mode, the cex n output toggles each time a match occurs between the pca counter and the module?s capture registers.
w78erd2/w78erd2a publication release date: february 14, 2007 - 49 - revision a10 11.4 pulse width modulator mode the pwm and ecom (ccapm) bits must be set to enable the pwm mode. enable 0 1 cexn - eccfn pwmn togn matn capnn cappn ecomn ccapmn, n=0~4 (dah~deh) pca timer/counter 000 0 ccapnh ccapnl 8-bit comparator cl 0 overflow cl < ccapnl cl >= ccapnl figure 11-5 pac pwm mode all of the modules have the same frequency because t hey share the same pca timer. the duty cycle of each module, however, is independently controll ed by the module?s capture register ccapln. when the value of the pca cl sfr is less than the value in ccapln, the output is low; when it is equal to or greater than the value in ccapln, the output is high. when cl overflows from ff to 00, ccapln is reloaded with the value in ccaphn. 11.5 watchdog timer the watchdog timer is a free-running timer that serv es as a system monitor. it is implemented in module 4, which can still be used for other modes if the watchdog timer is not needed. - eccf4 pwm4 tog4 mat4 capn4 capp4 ecom4 ccapm4(deh) 01 0 write to ccap4h write to ccap4l ccap4h ccap4l ch cl pca timer/counter 16-bit comparator enable match 0 1 0 cidl ecf cps0 cps1 - - - wdte cmod(d9h) xx module4 reset figure 11-6 pca watchdog timer mode the program first loads a 16-bit value into the com pare registers. then, like the other compare modes, this 16-bit value is compared to the pca timer val ue. if a match occurs, an internal reset is generated, but it does not make the rst pin go high.
w78erd2/w78erd2a - 50 - 12. hardware watchdog timer (one-time enabled with reset-out) the wdt is intended as a way to recover when t he cpu may be subject to software problem. the wdt consists of a 14-bit counter and the wdt reset (wdtrst) register located at 0a6h. the wdt is disabled at reset. to enable the wdt, user mu st write 01eh and 0e1h in sequence to wdtrst. once the wdt is enabled, it increments every mach ine cycle, while the oscillator is running, and there is no way to disable the wdt except through reset (either hardware reset or wdt overflow reset). the program must reset the counter by writing 01eh and 0e1h to wdtrst before the wdt counter reaches 3fffh (i.e., overfl ows). if it does overflow, it driv es a high pulse on the rst-pin. this pulse width is 98 source clocks in 12-clo ck mode or 49 source clocks in 6-clock mode. no external pull-down resistor or pull-up c apacitor is required on the reset pin. the wdt counter cannot be read or written. to ma ke the best use of the wdt, the wdt should be reset in sections of code that are periodically executed in time to prevent a wdt reset. 13. dual dptr the dual dptr structure is the way the chip s pecifies the address of an external data memory location. there are two 16-bit dptr registers that address external memory. the dps bit (auxr1, bit 0) switches between them, and it can be toggled quickl y by an inc auxr1 instruction. (auxr1, bit 2 cannot be written and is always read as a zero, so the inc auxr1 instruction does not affect the gf2 bit that is higher in the auxr1 register.) it is important to keep track of the value of the dps bit. for example, procedures and functions should save the dps bit before switching between dptr0 and dptr1 and restore the original value afterwards to prevent other c ode from using the wrong memory.
w78erd2/w78erd2a publication release date: february 14, 2007 - 51 - revision a10 14. timed-access protection the w78erd2 has features like timer clock sele cting by setting ckcon, software reset and isp function that are crucial to the proper operati on of the system. consequently, the sfr chpcon and ckcon, which control the functions, have restri cted write access to protect cpu from errant operation. the w78erd2 provides has a timed-acce ss protection scheme that controls write access to critical bits. in this scheme, protected bits have a timed writ e-enable window. a write is successful only if this window is active; otherwise, the write is disca rded. the write-enable window is opened in two steps. first, the software writes 87h to the register chpenr. this starts a counter, which expires in three machine cycles. then, if the software writes 59h to chpenr before the counter expires, the write- enable window is opened for three machine cycles. after three machine cycles, the window automatically closes, and the procedure must be repeated again to access protected bits. the suggested code for opening the write-enable window is chpenr reg 0f6h ; define new register chpenr, located at 0f6h mov chpenr, #87h mov chpenr, #59h five examples, some correct and some incorrect, of using timed-access protection are shown below.
w78erd2/w78erd2a - 52 - example 1: valid access mov chpenr, #87h ;3 m/c, note: m/c = machine cycles mov chpenr, #59h ;3 m/c mov ckcon, #00h ;3 m/c example 2: valid access mov chpenr, #87h ;3 m/c mov chpenr, #59h ;3 m/c nop ;1 m/c setb ewt ;2 m/c example 3: valid access mov chpenr, #87h ;3 m/c mov chpenr, #59h ;3 m/c orl ckcon, #01h ;3m/c example 4: invalid access mov chpenr, #87h ;3 m/c mov chpenr, #59h ;3 m/c nop ;1 m/c nop ;1 m/c clr md ;2 m/c example 5: invalid access mov chpenr, #87h ;3 m/c nop ;1 m/c mov chpenr, #59h ;3 m/c setb md ;2 m/c in the first three examples, the protected bits ar e written before the window closes. in example 4, however, the write occurs after the window has clos ed, so there is no change in the protected bit. in example 5, the second write to chpenr occurs four ma chine cycles after the first write, so the timed access window in not opened at all, and the write to the protected bit fails.
w78erd2/w78erd2a publication release date: february 14, 2007 - 53 - revision a10 15. in-system programming (isp) mode the w78erd2 is equipped with 64 kb of main flas h eprom (ap flash eprom) for the application program and 4 kb of auxiliary flash eprom (ld fl ash eprom) for the loader program. in normal operation, the microcontroller executes the code in the ap flash eprom. if the code in the ap flash eprom needs to be modified, however, the w78erd2 a llows the program to activate the in-system programming (isp) mode to modify it. the contents in the ap flash eprom can be modified by setting the chpcon register. the chpcon is read-only by default. the program must write two specific values, 87h and then 59h, sequentially to the chpenr register to enable the chpcon write attribute. writing chpenr register with any other values disables the write attribute. setting the bit chpcon.0 makes the w78erd2 enter isp mode when it wakes up from the next idle mode. it takes time to set this up in idle mode, however, so the program may use a timer interrupt to wake up the w78erd2 and enter isp mode after an appropriate amount of time in idle mode. to change the contents in the ap flash eprom, the existing contents must set the chpcon register and then enter idle mode. when the w78erd2 wakes up, it switches from ap flash eprom to ld flash eprom, clears the program counter, pushing 0000h to the first 2 bytes of stack memory and executes the interrupt service routine in the ld fl ash eprom. therefore, the first execution of reti instruction will make the program jump to 00h in the ld flash eprom. when the ap flash eprom has been updated, the w78erd2 offers a software reset to switch back to the ap flash eprom. setting chpcon bits 0, 1 and 7 to logic-1 creates a software reset to reset the cpu . a flowchart for the ld flash eprom program is shown at the end of this section. sfrah, sfral: the objective address of the on-chip flas h eprom in isp mode. sfrfah contains the high-order byte, and sfrfal contains the low-order byte. sfrfd: the program data in isp mode. sfrcn: the control byte for isp mode. sfrcn (c7) bit name function 7 - reserve. 6 wfwin on-chip flash eprom bank select for in-system programming. 0: 64-kb flash eprom bank is the destination for re-programming. 1: 4-kb flash eprom bank is the destination for re-programming. 5 oen flash eprom output enable. 4 cen flash eprom chip enable. 3, 2, 1, 0 ctrl[3:0] flash eprom control signals; see below.
w78erd2/w78erd2a - 54 - mode wfwin ctrl<3:0> oe n cen sfrah, sfral sfrfd erase 64kb ap flash eprom 0 0010 1 0 x x program 64kb ap flash eprom 0 0001 1 0 address in data in read 64kb ap flash eprom 0 0000 0 0 address in data out erase 4kb ld flash eprom 1 0010 1 0 x x program 4kb ld flash eprom 1 0001 1 0 address in data in read 4kb ld flash eprom 1 0000 0 0 address in data out
w78erd2/w78erd2a publication release date: february 14, 2007 - 55 - revision a10 start the algorithm of in-system programming enter in-system programming mode ? (conditions depend on user's application) setting control registers mov chpenr,#87h mov chpenr,#59h mov chpcon,#03h setting timer (about 1.5 us) and enable timer interrupt start timer and enter idle mode. (cpu will be wakened from idle mode by timer interrupt, then enter in-system programming mode) execute the normal application program no yes end cpu will be wakened by interrupt and re-boot from 4kb ldrom to execute the loader program. go part 1:aprom procedure of entering in-system programming mode figure 15-1 the algorithm of isp for ap rom
w78erd2/w78erd2a - 56 - part 2: 4kb ldrom procedure of updating the 64kb aprom go timer interrupt service routine: stop timer & disable interrupt is f04kboot mode? (chpcon.7=1) reset the chpcon register: mov chpenr,#87h mov chpenr,#59h mov chpcon,#03h no yes setting timer and enable timer interrupt for wake-up . (15 ms for erasing operation) setting erase operation mode: mov sfrcn,#22h (erase 64kb aprom) start timer and enter idle mode. (erasing...) end of erase operation. cpu will be wakened by timer interrupt. pgm pgm setting timer and enable timer interrupt for wake-up . (50us for program operation) end of programming ? get the parameters of new code (address and data bytes) through i/o ports, uart or other interfaces. is currently in the f04kboot mode ? setting control registers for programming: mov sfrah,#address_h mov sfral,#address_l mov sfrfd,#data mov sfrcn,#21h software reset cpu and re-boot from the 64kb aprom. mov chpenr,#87h mov chpenr,#59h mov chpcon,#83h end executing new code from address 00h in the 64kb aprom. hardware reset to re-boot from new 64 kb aprom. (s/w reset is invalid in h/w reboot mode) yes no yes no figure 15-2 the algorithm of isp for ld rom
w78erd2/w78erd2a publication release date: february 14, 2007 - 57 - revision a10 16. h/w reboot mode (boot from ldrom) by default, the w78erd2 boots up from the ap flash eprom after a power-on reset. sometimes, this is not desirable. h/w reboot mode forces the w78erd2 to use the ld flash eprom instead and execute in-system programmi ng procedures. enter h/w reboot mode using these settings. h/w reboot mode p4.3 p2.7 p2.6 option bit mode x l l bit4 = l h/w reboot l x x bit5 = l h/w reboot this might be implemented by connecting pins p2.6 and p2 .7 to switches or jumpers. for example, in a cd-rom system, p2.6 and p2.7 might be connec ted to the play and eject buttons on the panel. if the user wants to enter h/w reboot mode, the us er can press these two buttons at the same time and then turn on the power to force the w78erd2 to enter h/w reboot mode. after the power-on, releasing both buttons finishes t he in-system programming procedure. this mode can be accidentally activated, so be careful with the values of pins p2, p3, ale, e a and psen at reset . the reset timing for entering h/w reboot mode 1 p2.7 p2.6 rst 10us 20ms hi-z hi-z h/w reboot mode 2 p4.3 rst 10us 20ms hi-z figure 16-1
w78erd2/w78erd2a - 58 - 17. option bits register in the on-chip flash eprom writer programmi ng mode mode, the flash eprom can be programmed and verified repeatedly. until the code is ready, it can be protected by properly setting option bits. option bits control the initial configuration of w78erd2, including code protec tion, system clock mode selection (6t/12t), h/w reboot mode selection and oscillator control. lock bit this bit is used to protect the code in the w 78erd2. it may be set after the programmer finishes programming and verifies the sequence. once this bi t is set to logic-0, both the flash eprom data and option bits register cannot be accessed again.
w78erd2/w78erd2a publication release date: february 14, 2007 - 59 - revision a10 movc inhibit this bit is used to restrict the accessible region of the movc instruction. it can prevent a movc instruction in external program memory from reading the internal program code. when this bit is set to logic-0, a movc instruction in external program memory space can only access code in external memory, not in internal memory. a movc instructi on in internal program memory can always access both internal and external memory. if this bit is logic-1, there are no restrictions on movc. encryption this bit is used to enable and disable the encrypti on logic for code protection. once encryption is enabled, the data presented on port 0 is encoded via encry ption logic. this bit can be reset only by erasing the whole chip. oscillator control the gain of the on-chip oscillator amplifier can be reduc ed by bit b7 in the option bits register. if bit 7 is set to zero, the gain is cut in half. according the circuit in figure 20-1 , the values of r, c1 and c2 may need some adjustment when running at lower gain. furthermore, reducing the gai n by one-half may improperly affect an external crystal running at frequencies above 25 mhz.
w78erd2/w78erd2a - 60 - 18. electrical characteristics 18.1 absolute maximum ratings parameter symbol min. max. unit dc power supply v dd ? v ss -0.3 +6.0 v input voltage v in v ss -0.3 v dd +0.3 v operating temperature t a 0 70 c storage temperature t st -55 +150 c note: exposure to conditions beyond those listed under absolute ma ximum ratings may adversely affect the life and reliability of the device. 18.2 d.c. characteristics (v dd ? v ss = 5v 10%, t a = 25 c, fosc = 20 mhz, unless otherwise specified.) specification parameter sym. min. max. unit test conditions operating voltage v dd 4.5 5.5 v operating current i dd - 20 ma no load v dd = 5.5v idle current i idle - 10 ma idle mode v dd = 5.5v power down current i pwdn - 10 a power-down mode v dd = 5.5v input current p1, p2, p3, p4 i in1 -50 +10 a v dd = 5.5v v in = 0v or v dd input current rst i in2 0 +300 a v dd = 5.5v 0< v in w78erd2/w78erd2a publication release date: february 14, 2007 - 61 - revision a10 d.c. electrical charac teristics, continued specification parameter sym. min. max. unit test conditions input high voltage p0, p1, p2, p3, p4, ea v ih1 2.4 v dd +0.2 v v dd = 5.5v input high voltage rst v ih2 3.5 v dd +0.2 v v dd = 5.5v input high voltage xtal1 [*4] v ih3 3.5 v dd +0.2 v v dd = 5.5v output low voltage p1, p2, p3, p4 v ol1 - 0.45 v v dd = 4.5v i ol = +2 ma output low voltage p0, ale, psen [*3] v ol2 - 0.45 v v dd = 4.5v i ol = +4 ma sink current p1, p3, p4 isk1 4 8 ma v dd = 4.5v v in = 0.45v sink current p0, p2, ale, psen isk2 10 15 ma v dd = 4.5v v in = 0.45v output high voltage p1, p2, p3, p4 v oh1 2.4 - v v dd = 4.5v i oh = -100 a output high voltage p0, ale, psen [*3] v oh2 2.4 - v v dd = 4.5v i oh = -400 a source current p1, p2, p3, p4 isr1 -180 -300 a v dd = 4.5v v in = 2.4v source current p0, p2, ale, psen isr2 -8 -12 ma v dd = 4.5v v in = 2.4v notes: *1. rst pin is a schmitt-trigger input. *2. p0, ale and psen are tested in external-access mode. *3. xtal1 is a cmos input. *4. pins of p1, p2, p3 and p4 can source a transition cu rrent when they are being externally driven from 1 to 0. the transition current reaches its maximum value when v in is approximately 2v.
w78erd2/w78erd2a - 62 - 18.3 a.c. characteristics the ac specifications are a function of the particu lar process used to manufacture the part, the ratings of the i/o buffers, the capacitive load, and the internal routing capacitance. most of the specifications can be expressed in terms of multiple input clock periods (t cp ), and actual parts will usually experience less than a 20 ns variation. clock input waveform t t xtal1 f ch cl op, t cp parameter symbol min. typ. max. unit notes operating speed fop 0 - 40 mhz 1 clock period t cp 25 - - ns 2 clock high t ch 10 - - ns 3 clock low t cl 10 - - ns 3 notes: 1. the clock may be stopped indefinitely in either state. 2. the t cp specification is used as a reference in other specifications. 3. there are no duty cycle requirements on the xtal1 input. program fetch cycle parameter symbol min. typ. max. unit notes address valid to ale low t aas 1 t cp - ? - - ns 4 address hold from ale low t aah 1 t cp - ? - - ns 1, 4 ale low to psen low t apl 1 t cp - ? - - ns 4 psen low to data valid t pda - - 2 t cp ns 2 data hold after psen high t pdh 0 - 1 t cp ns 3 data float after psen high t pdz 0 - 1 t cp ns ale pulse width t alw 2 t cp - ? 2 t cp - ns 4 psen pulse width t psw 3 t cp - ? 3 t cp - ns 4 notes : 1. p0.0 ? p0.7, p2.0 ? p2.7 remain stable throughout entire memory cycle. 2. memory access time is 3 t cp . 3. data have been latched internally prior to psen going high. 4. " ? " (due to buffer driving delay and wire loading) is 20 ns.
w78erd2/w78erd2a publication release date: february 14, 2007 - 63 - revision a10 data read cycle parameter symbol min. typ. max. unit notes ale low to rd low t dar 3 t cp - ? - 3 t cp+ ? ns 1, 2 rd low to data valid t dda - - 4 t cp ns 1 data hold from rd high t ddh 0 - 2 t cp ns data float from rd high t ddz 0 - 2 t cp ns rd pulse width t drd 6 t cp - ? 6 t cp - ns 2 notes: 1. data memory access time is 8 t cp . 2. " ? " (due to buffer driving delay and wire loading) is 20 ns. data write cycle parameter symbol min. typ. max. unit ale low to wr low t daw 3 t cp - ? - 3 t cp + ? ns data valid to wr low t dad 1 t cp - ? - - ns data hold from wr high t dwd 1 t cp - ? - - ns wr pulse width t dwr 6 t cp - ? 6 t cp - ns note: " ? " (due to buffer driving delay and wire loading) is 20 ns. port access cycle parameter symbol min. typ. max. unit port input setup to ale low t pds 1 tcp - - ns port input hold from ale low t pdh 0 - - ns port output to ale t pda 1 tcp - - ns note: ports are read during s5p2, and output data becomes availabl e at the end of s6p2. the timing data are referenced to ale, since it provi des a convenient reference.
w78erd2/w78erd2a - 64 - 19. timing waveforms program fetch cycle s1 xtal1 s2 s3 s4 s5 s6 s1 s2 s3 s4 s5 s6 ale port 2 a0-a7 a0-a7 data a0-a7 code t a0-a7 data code port 0 psen pdh, t pdz t pda t aah t aas t psw t apl t alw data read cycle s2 s3 s5 s6 s1 s2 s3 s4 s5 s6 s1 s4 xtal1 ale psen data a8-a15 port 2 port 0 a0-a7 rd t ddh, t ddz t dda t drd t dar
w78erd2/w78erd2a publication release date: february 14, 2007 - 65 - revision a10 data write cycle s2 s3 s5 s6 s1 s2 s3 s4 s1 s5 s6 s4 xtal1 ale psen a8-a15 data out port 2 port 0 a0-a7 wr t t daw dad t dwr t dwd port access cycle xtal1 ale s5 s6 s1 data out t t port input t sample pda pdh pds
w78erd2/w78erd2a - 66 - 20. typical application circuits 20.1 external program memory and crystal ad0 a0 a0 a0 10 a1 9 a2 8 a3 7 a4 6 a5 5 a6 4 a7 3 a8 25 a9 24 a10 21 a11 23 a12 2 a13 26 a14 27 a15 1 ce 20 oe 22 o0 11 o1 12 o2 13 o3 15 o4 16 o5 17 o6 18 o7 19 27512 ad0 d0 3 q0 2 d1 4 q1 5 d2 7 q2 6 d3 8 q3 9 d4 13 q4 12 d5 14 q5 15 d6 17 q6 16 d7 18 q7 19 oc 1 g 11 74ls373 ad0 ea 31 xtal1 19 xtal2 18 rst 9 int0 12 int1 13 t0 14 t1 15 p1.0 1 p1.1 2 p1.2 3 p1.3 4 p1.4 5 p1.5 6 p1.6 7 p1.7 8 39 38 37 36 35 34 33 32 21 22 23 24 25 26 27 28 17 wr p0.0 p0.1 p0.2 p0.3 p0.4 p0.5 p0.6 p0.7 p2.0 p2.1 p2.2 p2.3 p2.4 p2.5 p2.6 p2.7 rd 16 psen 29 ale 30 txd 11 rxd 10 10 u 8.2 k v crystal c1 c2 r ad1 ad2 ad3 ad4 ad5 ad6 ad7 a8 ad1 ad2 ad3 ad4 ad5 ad6 ad7 gnd a1 a2 a3 a4 a5 a6 a7 a1 a2 a3 a4 a5 a6 a7 a8 a9 ad1 ad2 ad3 ad4 ad5 ad6 ad7 a10 a11 a12 a13 a14 a15 gnd a9 a10 a11 a12 a13 a14 a15 dd figure 20-1 crystal c1 c2 r 6 mhz 47p 47p - 16 mhz 30p 30p - 24 mhz 15p 15p - 32 mhz 10p 10p 6.8k 40 mhz 1p 1p 3 k above table shows the reference values for crystal applications. notes: 1. for c1, c2 and r components, see figure 20-1 2. the crystal should be as cl ose as possible to the xtal1 and xt al2 pins on the application board.
w78erd2/w78erd2a publication release date: february 14, 2007 - 67 - revision a10 20.2 expanded external data memory and oscillator 10 u 8.2 k v oscillator ea 31 xtal1 19 xtal2 18 rst 9 int0 12 int1 13 t0 14 t1 15 p1.0 1 p1.1 2 p1.2 3 p1.3 4 p1.4 5 p1.5 6 p1.6 7 p1.7 8 p0.0 39 p0.1 38 p0.2 37 p0.3 36 p0.4 35 p0.5 34 p0.6 33 p0.7 32 p2.0 21 p2.1 22 p2.2 23 p2.3 24 p2.4 25 p2.5 26 p2.6 27 p2.7 28 rd 17 wr 16 psen 29 a le 30 txd 11 rxd 10 a d0 a d1 a d2 a d3 a d4 a d5 a d6 a d7 a d0 a d1 a d2 a d3 a d4 a d5 a d6 a d7 a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 d0 3 q0 2 d1 4 q1 5 d2 7 q2 6 d3 8 q3 9 d4 13 q4 12 d5 14 q5 15 d6 17 q6 16 d7 18 q7 19 oc 1 g 11 74ls373 a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 10 9 8 7 6 5 4 3 a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a d0 a d1 a d2 a d3 a d4 a d5 a d6 a d7 11 12 13 15 16 17 18 19 d0 d1 d2 d3 d4 d5 d6 d7 a 8 a 9 a 10 a 11 a 12 a 13 a 14 25 24 21 23 26 1 20 2 a 8 a 9 a 10 a 11 a 12 a 13 a 14 ce gnd a 8 a 9 a 10 a 11 a 12 a 13 a 14 gnd 22 27 oe wr 20256 dd v dd figure 20-2
w78erd2/w78erd2a - 68 - 21. package dimensions 40-pin dip seating plane 1. dimension d max. & s include mold flash or tie bar burrs. 2. dimension e1 does not include interlead flash. 3. dimension d & e1 include mold mismatch and are determined at the mold parting line. 6. general appearance spec. should be based on final visual inspection spec. . 1.372 1.219 0.054 0.048 notes: symbol min. nom. max. max. nom. min. dimension in inch dimension in mm 0.050 1.27 0.210 5.334 0.010 0.150 0.016 0.155 0.018 0.160 0.022 3.81 0.406 0.254 3.937 0.457 4.064 0.559 0.008 0.120 0.670 0.010 0.130 0.014 0.140 0.203 3.048 0.254 3.302 0.356 3.556 0.540 0.550 0.545 13.72 13.97 13.84 17.01 15.24 14.986 15.494 0.600 0.590 0.610 2.286 2.54 2.794 0.090 0.100 0.110 a b c d e a l s a a 1 2 e b 1 1 e e 1 a 2.055 2.070 52.20 52.58 015 0.090 2.286 0.650 0.630 16.00 16.51 protrusion/intrusion. 4. dimension b1 does not include dambar 5. controlling dimension: inches. 15 0 e a a a c e base plane 1 a 1 e l a s 1 e d 1 b b 40 21 20 1 2 44-pin plcc 44 40 39 29 28 18 17 7 61 l c 1 b 2 a h d d e b e h e y a a 1 seating plane d g g e symbol min. nom. max. max. nom. min. dimension in inch dimension in mm a b c d e h e l y a a 1 2 e b 1 h d g g d e notes: on final visual inspection spec. 4. general appearance spec. should be based 3. controlling dimension: inches protrusion/intrusion. 2. dimension b1 does not include dambar flash. 1. dimension d & e do not include interlead 0.020 0.145 0.026 0.016 0.008 0.648 0.590 0.680 0.090 0.150 0.028 0.018 0.010 0.653 0.610 0.690 0.100 0.050 bsc 0.185 0.155 0.032 0.022 0.014 0.658 0.630 0.700 0.110 0.004 0.508 3.683 0.66 0.406 0.203 16.46 14.99 17.27 2.296 3.81 0.711 0.457 0.254 16.59 15.49 17.53 2.54 1.27 4.699 3.937 0.813 0.559 0.356 16.71 16.00 17.78 2.794 0.10 bsc 16.71 16.59 16.46 0.658 0.653 0.648 16.00 15.49 14.99 0.630 0.610 0.590 17.78 17.53 17.27 0.700 0.690 0.680
w78erd2/w78erd2a publication release date: february 14, 2007 - 69 - revision a10 44-pin pqfp seating plane 11 22 12 see detail f e b a y 1 a a l l 1 c e e h 1 d 44 h d 34 33 detail f 1. dimension d & e do not include interlead flash. 2. dimension b does not include dambar protrusion/intrusion. 3. controlling dimension: millimeter 4. general appearance spec. should be based on final visual inspection spec. 0.254 0.101 0.010 0.004 notes: symbol min. nom. max. max. nom. min. dimension in inch dimension in mm a b c d e h d h e l y a a l 1 1 2 e 0.006 0.152 --- 0.002 0.075 0.01 0.081 0.014 0.087 0.018 1.90 0.25 0.05 2.05 0.35 2.20 0.45 0.390 0.025 0.063 0.003 0 7 0.394 0.031 0.398 0.037 9.9 0.80 0.65 1.6 10.00 0.8 10.1 0.95 0.398 0.394 0.390 0.530 0.520 0.510 13.45 13.2 12.95 10.1 10.00 9.9 7 0 0.08 0.031 0.01 0.02 0.25 0.5 --- --- --- --- --- 2 0.025 0.036 0.635 0.952 0.530 0.520 0.510 13.45 13.2 12.95 0.051 0.075 1.295 1.905
w78erd2/w78erd2a - 70 - 22. application note 22.1 in-system programming (isp) software examples this application note illustrates the in-syste m programmability of the winbond w78erd2 flash eprom microcontroller. in this example, t he microcontroller boots from 64 kb ap flash eprom bank and waits for a key to enter isp mode to re -program the 64-kb ap flash eprom. while in isp mode, the microcontroller executes the loader pr ogram in the 4-kb ld flash eprom. the loader program erases the 64-kb ap flas h eprom and then reads the new code from an external sram buffer (or through other interfaces ) to update the 64-kb ap flash eprom. example 1: ;******************************************************************************************************************* ;* example of 64k ap flash eprom program: progr am will scan the p1.0. if p1.0 = 0, enters ;* in-system programming mode for updating the cont ent of ap flash eprom code else executes the ;* current rom code. ;* xtal = 40 mhz ;******************************************************************************************************************* .chip 8052 .ramchk off .symbols chpcon equ bfh chpenr equ f6h sfral equ c4h sfrah equ c5h sfrfd equ c6h sfrcn equ c7h org 0h ljmp 100h ; jump to main program ;************************************************************************ ;* timer0 service vector org = 000bh ;************************************************************************ org 00bh clr tr0 ; tr0 = 0, stop timer0 mov tl0, r6 mov th0, r7 reti ;************************************************************************ ;* 64k ap flash eprom main program ;************************************************************************ org 100h main_64k: mov a, p1 ; scan p1.0 anl a, #01h cjne a, #01h, program_64k ; if p1.0 = 0, enter in-system programming mode jmp normal_mode program_64k: mov chpenr, #87h ; chpenr = 87h, chpcon register wrte enable mov chpenr, #59h ; chpenr = 59h, chpcon register write enable mov chpcon, #03h ; chpcon = 03h, enter in-system programming mode mov tcon, #00h ; tr = 0 timer0 stop mov ip, #00h ; ip = 00h
w78erd2/w78erd2a publication release date: february 14, 2007 - 71 - revision a10 mov ie, #82h ; timer0 interrupt enable for wake-up from idle mode mov r6, #f0h ; tl0 = f0h mov r7, #ffh ; th0 = ffh mov tl0, r6 mov th0, r7 mov tmod, #01h ; tmod = 01h, set timer0 a 16-bit timer mov tcon, #10h ; tcon = 10h, tr0 = 1, go mov pcon, #01h ; enter idle mode for launching the in-system ; programmability ;******************************************************************************** ;* normal mode 64kb ap flash eprom program: depending user's application ;******************************************************************************** normal_mode: . ; user's application program . . . example 2: ;***************************************************************************************************************************** ;* example of 4kb ld flash eprom program: this l oader program will erase the 64kb ap flash eprom first, ;* then reads the new code from external sram and program them into 64kb ap flash eprom bank. ;* xtal = 40mhz ;***************************************************************************************************************************** .chip 8052 .ramchk off .symbols chpcon equ bfh chpenr equ f6h sfral equ c4h sfrah equ c5h sfrfd equ c6h sfrcn equ c7h org 000h ljmp 100h ; jump to main program ;************************************************************************ ;* 1. timer0 service vector org = 0bh ;************************************************************************ org 000bh clr tr0 ; tr0 = 0, stop timer0 mov tl0, r6 mov th0, r7 reti ;************************************************************************ ;* 4kb ld flash eprom main program ;************************************************************************ org 100h main_4k: mov sp, #c0h ; be initial sp register
w78erd2/w78erd2a - 72 - mov chpenr, #87h ; chpenr = 87h, chpcon write enable. mov chpenr, #59h ; chpenr = 59h, chpcon write enable. mov a, chpcon anl a, #80h cjne a, #80h, update_64k; check h/w reboot mode ? mov chpcon, #03h ; chpcon = 03h, enable in-system programming. mov chpenr, #00h ; disable chpcon write attribute mov tcon, #00h ; tcon = 00h, tr = 0 timer0 stop mov tmod, #01h ; tmod = 01h, set timer0 a 16bit timer mov ip, #00h ; ip = 00h mov ie, #82h ; ie = 82h, timer0 interrupt enabled mov r6, #f0h mov r7, #ffh mov tl0, r6 mov th0, r7 mov tcon, #10h ; tcon = 10h, tr0 = 1, go mov pcon, #01h ; enter idle mode update_64k: mov chpenr, #00h ; disable chpcon write-attribute mov tcon, #00h ; tcon = 00h, tr = 0 tim0 stop mov ip, #00h ; ip = 00h mov ie, #82h ; ie = 82h, timer0 interrupt enabled mov tmod, #01h ; tmod = 01h, mode1 mov r6, #3ch ; set wake-up time for erase operation, about 15 ms. depending ; on user's system clock rate. mov r7, #b0h mov tl0, r6 mov th0, r7 erase_p_4k: mov sfrcn, #22h ; sfrcn(c7h) = 22h erase 64k mov tcon, #10h ; tcon = 10h, tr0 = 1, go mov pcon, #01h ; enter idle mode (for erase operation) ;********************************************************************* ;* blank check ;********************************************************************* mov sfrcn, #0h ; read 64kb ap flash eprom mode mov sfrah, #0h ; start address = 0h mov sfral, #0h mov r6, #fbh ; set timer for read operation, about 1.5 s. mov r7, #ffh mov tl0, r6 mov th0, r7 blank_check_loop: setb tr0 ; enable timer 0 mov pcon, #01h ; enter idle mode mov a, sfrfd ; read one byte cjne a, #ffh, blank_check_error inc sfral ; next address mov a, sfral jnz blank_check_loop
w78erd2/w78erd2a publication release date: february 14, 2007 - 73 - revision a10 inc sfrah mov a, sfrah cjne a, #0h, blank_check _loop ; end address = ffffh jmp program_64krom blank_check_error: mov p1, #f0h mov p3, #f0h jmp $ ;******************************************************************************* ;* re-programming 64kb ap flash eprom bank ;******************************************************************************* program_64krom: mov dptr, #0h ; the address of new rom code mov r2, #00h ; target low byte address mov r1, #00h ; target high byte address mov dptr, #0h ; external sram buffer address mov sfrah, r1 ; sfrah, target high address mov sfrcn, #21h ; sfrcn(c7h) = 21 (program 64k) mov r6, #5ah ; set timer for programming, about 50 s. mov r7, #ffh mov tl0, r6 mov th0, r7 prog_d_64k: mov sfral, r2 ; sfral(c4h) = low byte address movx a, @dptr ; r ead data from external sram buffer mov sfrfd, a ; sfrfd(c6h) = data in mov tcon, #10h ; tcon = 10h, tr0 = 1, go mov pcon, #01h ; enter idle mode (prorgamming) inc dptr inc r2 cjne r2, #0h, prog_d_64k inc r1 mov sfrah, r1 cjne r1, #0h, prog_d_64k ;***************************************************************************** ; * verify 64kb ap flash eprom bank ;***************************************************************************** mov r4, #03h ; error counter mov r6, #fbh ; set timer for read verify, about 1.5 s. mov r7, #ffh mov tl0, r6 mov th0, r7 mov dptr, #0h ; the start address of sample code mov r2, #0h ; target low byte address mov r1, #0h ; target high byte address mov sfrah, r1 ; sfrah, target high address mov sfrcn, #00h ; sfrcn = 00 (read rom code) read_verify_64k: mov sfral, r2 ; sfral(c4h) = low address
w78erd2/w78erd2a - 74 - mov tcon, #10h ; tcon = 10h, tr0 = 1, go mov pcon, #01h inc r2 movx a, @dptr inc dptr cjne a, sfrfd, error_64k cjne r2, #0h, read_verify_64k inc r1 mov sfrah, r1 cjne r1, #0h, read_verify_64k ;****************************************************************************** ;* programming completly, software reset cpu ;****************************************************************************** mov chpenr, #87h ; chpenr = 87h mov chpenr, #59h ; chpenr = 59h mov chpcon, #83h ; chpcon = 83h, software reset. error_64k: djnz r4, update_64k ; if error occurs, repeat 3 times. . ; in-system programming fail, user's process to deal with it. . . . 22.2 how to use programmable counter array please go to winbond?s website at http://www.winbond.com.tw fort the application note.
w78erd2/w78erd2a publication release date: february 14, 2007 - 75 - revision a10 23. revision history version date page description a1 june 2004 - initial issued 38 modify the content of pca a2 august 2004 74 add the application of pca a3 sep. 30, 2004 38 add enhanced full duplex serial port with framing error detection and automatic address recognition a4 april 20, 2005 72 add important notice a5 june 2, 2005 4 17 22 38 to add lead free part no. of packages. correct gf3 to gf2 in auxr1 correct xiconh add programmable timers/counters. a6 sep. 5, 2005 - 49 re-organize document. add a section of timed-access protection a7 october 2, 2006 remove block diagram a8 december 4, 2006 3 remove all leaded package parts a9 december 15, 2006 32 correct the interrupt vector of int2 & int3. a10 february 14, 2007 46 correct cmod(d8h) to cmod(d9h)
w78erd2/w78erd2a - 76 - important notice winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgi cal implantation, atomic energy control instruments, airplane or spaceship instrument s, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. further more, winbond products are not intended for applications wherein failure of winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify winbond for any damages resulting from such improper use or sales. headquarters no. 4, creation rd. iii, science-based industrial park, hsinchu, taiwan tel: 886-3-5770066 fax: 886-3-5665577 http://www.winbond.com.tw/ taipei office tel: 886-2-8177-7168 fax: 886-2-8751-3579 winbond electronics corporation america 2727 north first street, san jose, ca 95134, u.s.a. tel: 1-408-9436666 fax: 1-408-5441798 winbond electronics (h.k.) ltd. no. 378 kwun tong rd., kowloon, hong kong fax: 852-27552064 unit 9-15, 22f, millennium city, tel: 852-27513100 please note that all data and specifications are subject to change without notice. all the trademarks of products and companies mentioned in this datasheet belong to their respective owners. winbond electronics (shanghai) ltd. 200336 china fax: 86-21-62365998 27f, 2299 yan an w. rd. shanghai, tel: 86-21-62365999 winbond electronics corporation japan shinyokohama kohoku-ku, yokohama, 222-0033 fax: 81-45-4781800 7f daini-ueno bldg, 3-7-18 tel: 81-45-4781881 9f, no.480, rueiguang rd., neihu district, taipei, 114, taiwan, r.o.c.

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